The original 'arch_pm_s2ram_resume' implementation saved lr on the stack
using 'push {lr}' and restored it using 'pop {lr}'. However, the Thumb-1
'pop' does not support lr as a target register, so this code would not
compile for ARMv6-M or ARMv8-M Baseline. r0 was added to these push/pop
later in 2590c48d40.
In 474d4c3249, arch_pm_s2ram* functions were
modified to no longer use the stack, which incidentally "fixed" this issue.
b4fb5d38eb reverted this commit and brought
back 'pop {r0, lr}' as-is, without taking compatibility into account.
Modify the sequence to use "pop {r0, pc}" which is supported on all
ARM M-profile implementations (v6/v7/v8 Baseline/v8 Mainline), and
add comments to (hopefully) prevent this issue from re-appearing.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
On the Xilinx MPSoC (Cortex-R5) platform, erratic operation was often
seen when an operation which disabled the dcache, such as sys_reboot,
was performed. Usually this manifested as an undefined instruction trap
due to the CPU jumping to an invalid memory address.
It appears the problem was due to dirty cache lines being present at the
time the cache is disabled. Once the cache is disabled, the CPU will
ignore the cache contents and read the possibly out-of-date data in main
memory. Likewise, since the cache was being cleaned after it was already
disabled, if the CPU had already written through changes to some memory
locations, cleaning the cache at that point would potentially overwrite
those changes with older data.
The fact that the arch_dcache_flush_and_invd_all function was being
called to do the cleaning and invalidation also contributed to this
problem, because it is a non-inline function which means the compiler
will generate memory writes to the stack when the function is called and
returns. Corruption of the stack can result in the CPU ending up jumping
to garbage addresses when trying to return from functions.
To avoid this problem, the cache is now cleaned and invalidated prior to
the dcache being disabled. This is done by directly calling the
L1C_CleanInvalidateDCacheAll function, which, as it is declared as force
inline, should help ensure there are no memory accesses, which would
populate new cache lines, between the cache cleaning and disabling the
cache.
Ideally, for maximum safety, the cache cleaning and cache disabling
should be done in assembler code, to guarantee that there are no memory
accesses generated by the compiler during these operations. However, the
present change does appear to solve this issue.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Add display support for the st7789v LCD controller.
Automatically enable the LCD backlight at boot
to use the display sample as is,
because the LCD backlight is normally off.
Signed-off-by: Samuel Quiniou <samuel.quiniou@rtone.fr>
The current implementation of the identity check fails if multiple DCO
signoff lines are present and the first instance of the signoff line
does not belong to the author of the commit. This patch proposes a solution
that allows patches with multiple DCO signoff lines to pass the identity
check, regardless of the order of the signoff lines.
Signed-off-by: Mirai SHINJO <oss@mshinjo.com>
Moved index of analog input used in test from source
code to Kconfig option to simplify adding new targets.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
Added set of analog pins for nRF54L20 COMP and LPCOMP.
Moved the array of analong pins for both comparator
variants to avoid code duplication.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
The code invoking nrfutil was not checking the return code of the
subprocess, which meant that if the underlying tool was exiting with a
failure error code it remained undetected.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
This file previously defined an MPU access permission mode of 0x7 which
corresponded to privileged read-only, unprivileged read-only, similar to
mode 0x6. However, it appears that at least Cortex-R5 does not support
this mode, defining 0x7 as UNP (Unpredictable) or a value which should
not be used.
This value was in turn referenced by the REGION_FLASH_ATTR macro, which
caused the offending value to be used when a memory region was declared
as DT_MEM_ARM(ATTR_MPU_FLASH) in the device tree, causing such regions
to not work properly on Cortex-R5.
Since 0x6 is supported by both Cortex-M and Cortex-R and does the same
thing, there is no reason to use 0x7. Remove the RO_Msk definition which
referenced it, and change REGION_FLASH_ATTR to use P_RO_U_RO_Msk instead.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Error checking of otIp6AddUnicastAddress() and
otIp6SubscribeMulticastAddress() was added recently, however it wasn't
taken into account that those APIs return an error on attempt to
register an IPv6 address that is already present on the OT interface.
Therefore, add more specific error checks, to return silently in case
address was already present.
As those two APIs are not very consistent, and otIp6AddUnicastAddress()
returns OT_ERROR_INVALID_ARGS in such cases, add an extra check if the
address is already present before attempting to register the address.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Changed to define ambiq spi/i2c dma mode as a binding property
instead of kconfig macros, making it more flexible for different
spi/i2c instances.
Signed-off-by: Hao Luo <hluo@ambiq.com>
The x_nucleo_gfx01m2 is an evaluation shield sold by
STMicroelectronics. It features a MIPI DBI SPI serial TFT LCD display
and a SPI NOR Flash for graphical assets storage. A button joystick
can be used to control the GUI.
Signed-off-by: Christian Rask <christianrask2@gmail.com>
Most SPI NOR flash devices support a "fast read" command which uses
dummy bits between the address and the start of the data transfer. In
many cases, the maximum SPI clock speed of the device is lower for the
regular read command due to the limited time between the address and
data phases, so using the fast read command will remove this restriction
and allow for faster transfers.
Add a device tree flag to indicate that fast reads should be used for
the device.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Some Micron (and possibly other) SPI NOR devices implement a flag status
register which provides more information on the success/failure of erase
and program operations. In addition to better error checking, some of
these devices actually don't function properly if the flag status
register is not read after a program operation (subsequent reads will
only return 0xFF bytes).
Add a device tree parameter to indicate that the flag status register is
supported. When specified, the flag status register will be used for
ready/error checks rather than the standard status register.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
This driver was providing SPI buffers for both TX and RX on the data
payload portion of read transfers, even though the TX buffer is not
meaningful in these cases. As well as being less efficient, this also
caused likely uninitialized data to be transferred to the device, which
is possibly problematic.
Update to not include the TX buffer for the read data payload SPI
transfer, so that the SPI driver can generate dummy TX data internally.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Add the 4Bytes program mode to the stm32_ospi driver
to enter 4-Byte Address Mode (SPI_NOR_CMD_4BA) when flash is supporting it.
This is given by the JESD216 SFDP table.
Based on the stm32 qspi driver.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Code responsible for internal capacitor values containted
leftover workarounds in the calculations after PS update.
Removed redundant conversions and cleaned up both code
and comments to align both LFXO and HFXO calculation.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
The original Wi-Fi certificates are from WFA. Now replace them with
certificates that generated by myself. These certificates use
sha384WithRSAEncryption signature algorithm, and use 3072 bit RSA
public-key.
Signed-off-by: Maochen Wang <maochen.wang@nxp.com>
The value read from unwritten areas of Renesas RAxxx SoCs data
flash is undefined. To prevent reading unwritten areas a
blank check command is performed first. If the area is blank, we
return dummy data so it behaves the same as other flash devices.
Signed-off-by: Jeremy Dick <jdick@pivotint.com>
Add an erased-undefined property for Renesas RA series MCUS
data flash that will read back undefined values when erased
Signed-off-by: Jeremy Dick <jdick@pivotint.com>
The standstill detection logic now stands corrected. Moving would
be indicated when the standstill bit is not zero.
Signed-off-by: Dipak Shetty <shetty.dipak@gmx.com>
