This config CPU_CORTEX_M_HAS_DWT, is to avoid the
pragma message "Null-Pointer exception detection cannot
be configured on un-mapped flash areas"
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The AN547 is a Soft Macro Model implementation of the SSE-300 subsystem
with Ethos-U55 and Cortex-M55 components targeting the MPS3 board.
The SoC support is based on the AN521 MPS2+ support that already exists
in Zephyr.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In NPCX chips, System Configuration module can configure not only
pinctrl but also misc. functionality such as glue and flash write
protection. This change moves the scfg driver from the pinctrl folder
to soc/arm/nuvoton_npcx/common and renames it to avoid confusion.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This CL solves an interrupt storm caused by plenty of host access
messages when system is in S0. It only turns on the host access
interrupt before ec enters sleep and turns it off after leaving
sleep.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add SoC support to enable Cypress PSoC-6 pinctrl. This add devicetree
macros to handle pinctrl nodes and SoC GPIO methods to configure pins.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
CORTEX_M_SYSTICK should be disabled if LPTIM is selected.
Current implementation is not efficient to do so.
Rework the way the dependency is stated.
Fixes#33342
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add GPIO driver for QuickLogic EOS S3 SoC.
Co-authored-by: Jan Kowalewski <jkowalewski@antmicro.com>
Signed-off-by: Wojciech Tatarski <wtatarski@antmicro.com>
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
In some stm32 series systick was disabled in order to
allow alternate use of lptim timer as kernel low power ticker.
Doing this, dts based definition of CORTEX_M_SYSTICK Kconfig symbol
is disabled and CORTEX_M_SYSTICK was redefined with 'default y'
in stm32 soc files which makes things more complex to handle to
alternate with LPTIM activation.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This CL prevents changing data content in the write function of host
interface by declaring it as constant pointer.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
All users of ATMEL_SAM0_DT_INST_DMA_NAME are now using
ATMEL_SAM0_DT_INST_DMA_CTLR so we can remove the macro.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add a macro similar to ATMEL_SAM0_DT_INST_DMA_NAME but instead
provides the devicetree node back via DT_INST_DMAS_CTLR_BY_NAME
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Use kinetis SIM clock divider options set in device tree
instead of hardcoded values.
The kl25z device tree did not previously define a MCG node.
This has now been added with the general "nxp,kinetis-mcg"
binding.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
Use kinetis SIM clock divider options set in device tree
instead of kconfig.
The kv5x device tree originally used the undefined
"nxp,kv58-mcg" binding for the MCG node. This has been
replaced by the general "nxp,kinetis-mcg" binding.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
Use kinetis SIM clock divider options set in device tree
instead of kconfig.
Both the kw40z and kw41z device tree originally used an
undefined "nxp,kw41z-mcg" binding for the MCG node.
This has been replaced with the general "nxp,kinetis-mcg"
binding instead.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
SYSCLK_DEFAULT_IOSC_HZ and BUSCLK_DEFAULT_IOSC_HZ are
not used anywhere in the tree and can be removed
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
New power states have more granularity than deep sleep and sleep
states. Just get rid of this and keep the same behavior for now.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Maximum GIC SPI is 228, so maximum INTID is 228 + 32 = 260.
So, _sw_isr_table needs to support 260 entries
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Update register addresses and NVIC/GIC interrupt numbers
according to the latest viper RTL version.
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
There is no strict reason to use assembly for the reset routine. Move as
much code as possible to C code using the proper helpers.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The name for registers and bit-field in the cpu.h file is incoherent and
messy. Refactor the whole file using the proper suffixes for bits,
shifts and masks.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Enable the driver for the Kinetis Digital-to-Analog (DAC) modules
present in the NXP Kinetis K2x SoC series.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
Add some helper macros that will be convenient to use from device
drivers for accessing and error checking pin mux information in the
devicetree:
- NRF_DT_PSEL(): get a PSEL value out of the DT from either a
'foo-pin' or a 'foo-gpios' style property.
- NRF_DT_PSEL_CHECK_NOT_BOTH(), NRF_DT_PSEL_CHECK_EXACTLY_ONE():
helpers for checking that a given devicetree is OK according to
different criteria for setting PSEL properties (NAND or XOR on
whether the properties exist, respectively).
See comments in the patch for more details.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Add the declaration and check of debug interface register.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: Ib8ecd53f1d6139613f39243aee83bdd75a30f5be
In NPCX7 series, it contains two tachometer (TACH) modules that contains
two Independent timers (counter 1 and 2). They are used to capture a
counter value when an event is detected via the external pads (TA or
TB).
The CL also includes:
— Add npcx tachometer device tree declarations.
— Zephyr sensor api implementation for tachometer.
— Enable "tach1" device in npcx7m6fb.dts for testing.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Since the uart device clock will be stopped after ec entered sleep or
deep sleep state and restore its clock automatically, there is no need
to implement code for suspending and resuming devices manually.
The driver still needs to check the current status of uart device when
it wants to change its power state to LOW or SUSPEND power state. It is
crucial to forbid ec enters sleep or deep sleep state when uart device
is busy with transmitting data. Or we will observe broken characters on
the uart console.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces power management driver that improves the efficiency
of ec operation by adjusting the chip’s power consumption to the level
of activity required by the application in npcx series.
The following list summarizes the main properties of the various chip
power states. Please refer the power.c file for more detail.
Main power states in npcx series include:
- Active: Core, RAM and modules operate at the clocks generated by PLL.
- Idle: Enter this state when the Core executes WFI or WFE instruction.
- Sleep: clock is stopped for most of modules but PLL is enabled.
- Deep Sleep: As Sleep mode but PLL is disabled.
- Standby: All power rails are turned off besides standby and battery
power rails.
And this CL implements one power state, PM_STATE_SUSPEND_TO_IDLE, with
two sub-states for Zephyr power management system.
Sub-state 0 - "Deep Sleep" mode with “Instant” wake-up if residency
time is greater or equal to 1 ms
Sub-state 1 - "Deep Sleep" mode with "Standard" wake-up if residency
time is greater or equal to 201 ms
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces a kernel device driver implemented by the internal
64/32-bit timers in Nuvoton NPCX series. Via these two kinds of timer,
the driver provides an standard "system clock driver" interface.
It includes:
- A system timer based on an ITIM64 (Internal 64-bit timer) instance,
clocked by APB2 which freq is CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
- Its prescaler is set to 1 and provide the kernel cycles reading
without handling overflow mechanism.
- A event timer based on an ITIM32 (Internal 32-bit timer) instance,
clocked by LCLK which frequency is 32KHz and still activated when ec
entered "idle/deep idle" power state for better power consumption.
- Its prescaler is set to 1 and provide timeout event mechansim.
- Compensate system timer which clock is gating for better power
consumption after ec left"idle/deep idle" power state.
This CL passed starve, timer_api, and timer_monotonic test suites.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
stm32wb and stm32l4 are devices which supports the low power
from the Kernel PM, so is the PM_DEVICE defined.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
In case the policy is not available or defined by th application
the pm_policy_low_power_devices is still valid
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The clock configuration is restored by the stm32_clock_control_init
function of the clock_stm32_ll_common driver
when exiting the low power mode
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Francois Ramu <francois.ramu@st.com>
In case the policy is not available or defined by th application
the pm_policy_low_power_devices is still valid
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The clock configuration is restored by the stm32_clock_control_init
function of the clock_stm32_ll_common driver
when exiting the low power mode.
Keeping the stm32wbxx_ll_utils.h in case the PLL is used for wb.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Erratum 19 applies to earlier revisions of nRF5340 DK,
which are no longer supported in the tree, so we can
remove the code that handles it.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add Kconfig options to signify that the nRF5340
HW has support for QDEC instances. Select the
options in the nRF5340 Application core definition.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This driver missed #32228 PR that converted STM32 drivers
to use DEVICE_DT_GET for clock activation.
Due to the renaming of STM32_CLOCK_CONTROL_NAME to
STM32_CLOCK_CONTROL_NODE, driver could not compile anymore
Fix this.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Remove support for the Musca-A board. This board is rarely used, few
are available and superceded by Musca-B and Musca-S.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The NPCX clock driver was already using devicetree, just need to make a
small tweak to use DEVICE_DT_INST_DEFINE and update NPCX_CLK_CTRL_NAME
to match the label for the "nuvoton,npcx-pcc" clock controller.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add ESPI SAF features to the Microchip eSPI driver as
a separate file. ESPI SAF depends upon the core eSPI
driver adding the ability to attach the system SPI
flash to the EC eSPI endpoint instead of the host
eSPI controller.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
