Add the pinctrl state name (default) for the CAN peripherals.
Changes performed based on the script proposed in
"boards: arm: stm32: add pinctrl state name for UART peripheral"
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add the pinctrl state name (default) for the I2C peripherals.
Changes performed based on the script proposed in
"boards: arm: stm32: add pinctrl state name for UART peripheral"
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add the pinctrl state name (default) for the CAN peripherals.
Changes performed based on the script proposed in
"boards: arm: stm32: add pinctrl state name for UART peripheral"
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add the pinctrl state name (default) for the CAN peripherals.
Changes performed based on the script proposed in
"boards: arm: stm32: add pinctrl state name for UART peripheral"
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add the pinctrl state name (default) for the ADC peripherals.
Changes performed based on the script proposed in
"boards: arm: stm32: add pinctrl state name for UART peripheral"
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add the pinctrl state name (default) for the UART/USART/LPUART
peripherals. Changes performed using the following Python script run
from the repository root:
```
from pathlib import Path
import re
for fpath in Path(".").glob("boards/arm/**/*.dts"):
lines = open(fpath).readlines()
is_stm32 = False
for line in lines:
if "stm32" in line:
is_stm32 = True
break
if not is_stm32:
continue
with open(fpath, "w") as f:
for line in lines:
f.write(line)
m = re.match(r"(\s+)pinctrl-0.*us?art.*", line)
if m:
f.write(m.group(1) + "pinctrl-names = \"default\";\n")
```
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Enable the pin control driver on all STM32 based boards. The following
script has been used to do this task:
```
from pathlib import Path
import re
for fpath in Path(".").glob("boards/arm/**/*_defconfig"):
lines = open(fpath).readlines()
is_stm32 = False
for line in lines:
if "CONFIG_SOC_SERIES_STM32" in line:
is_stm32 = True
break
if not is_stm32:
continue
lines += ["\n", "# enable pin controller\n", "CONFIG_PINCTRL=y\n"]
with open(fpath, "w") as f:
f.writelines(lines)
```
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Failed to flash blinky example to stock nucleo_wl55jc due to default
application entering low power mode using WFI. To connect to a sleeping
stm32wl55 a system reset is required.
Signed-off-by: Jelle De Vleeschouwer <jelledevleeschouwer@gmail.com>
* With existence of Adafruit Qt Py boards, and upcoming wireless
Xiao from Seeeduino, define nexus node and peripheral node
labels for use with shields that accept any Xiao format board.
* Adds `&xiao_d`, `&xiao_spi`, `&xiao_i2c` and `&xiao_serial` generic
node labels.
* Add new 'seeed-xioa-header.yaml` to document new nexus node.
Signed-off-by: Peter Johanson <peter@peterjohanson.com>
This sets the commonly used serial port alias for blackmagicprobe, as
well as the flag to reset on connect, so that flashing works in low
power.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
Add the power state configs so that the board can be used with suspend
to idle out of the box. This is the same config as the one in
nucleo_wl55jc.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
The TFM build directory path is hardcoded in many places.
In order to support out-of-tree secure partitions the output path
has to be known in potentially out-of-tree build scripts.
This could potentially break out-of-tree build scripts if the
location of the build directory was changed.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
For reStructuredText, continuing text in a numbered list must be aligned
to the first line.
These lines are searched by the following regex:
ag '#\. .*\n[^ #\n]' **/*.rst
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Despite the "F4" prefix, GD32F403 is an SoC with significant differences
compared to other F4 MCUs:
- It has a completely different HAL
- It has significant hardware differences, for example, the pinctrl
mechanism uses AFIO (all others use AF)
The grouping principles applied to other similar vendors such as ST
can't be applied for GD32 due to these reasons, so the approach taken
here is to define series based on the used HAL. A different HAL likely
means that there are significant hardware differences between, e.g. F403
and F405. The vendor likely chose a confusing naming scheme, but we need
to deal with it.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The Flexspi memory address defines the location of the externally
attached flash to the MXRT600 based board. The flexspi has two
different memory spaces for secure and non-secure access that are
not aligned for the Flexspi register space and the memory map
address space. The normal method of handling this via the two
different dts files for secure/non-secure is not able to handle
this because a base address is applied uniformly across multiple
reg items.
Changes include:
- pull flexspi out of peripherals block to allow it to be explicitly
expressed in the respective secure/non-secure SOC DTS files.
- move the flash size definition to the board level definition and
use the size of the actual flash device found on the board.
:
Signed-off-by: David Leach <david.leach@nxp.com>
These boards try to configure CDC ACM UART as backend used
by the console driver. CONFIG_USB_UART_CONSOLE has no more
influence to console driver any and can be removed.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Prescaler was misplaced in pwm binding, instead of timers binding.
For example, TIM6/TIM7 doesn't have PWM capability,
but have a prescaler.
This change also prepares the introduction of timer based counter
(which requires prescaler at timer level)
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Updates to MEC172x eSPI driver to support ACPI shared
memory region and EC Host Command Subsystem through
ACPI_EC1 and Embedded Memory Interface (EMI).
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
- Fix the system clock frequency: should be 111.1 MHz instead
of 100 MHz.
- Set ticks per second to 1000 for higher system clock precision.
- Set QEMU icount shift value to 3 so that one instruction gets
executed every 2^3 = 8 ns.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@Weidmueller.com>
Refactors all of the on-chip GPIO drivers to use a shared driver class
initialization priority configuration, CONFIG_GPIO_INIT_PRIORITY, to
allow configuring GPIO drivers separately from other devices. This is
similar to other driver classes like I2C and SPI.
Most drivers previously used CONFIG_KERNEL_INIT_PRIORITY_DEFAULT or
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, therefore the default for this new
option is the lower of the two, which means earlier initialization.
Driver-specific options for off-chip I2C- or SPI-based GPIO drivers are
left intact because they often need to be initialized at a different
priority than on-chip GPIO drivers.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Currently there is no way to support running a board on multiple
emulation platforms nor to choose a desired emulation platform for the
simulation to be run on. This commit introduces a new
SUPPORTED_EMU_PLATFORMS list, which defines available emulation
platforms for a given board.
Fixes#12375.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Always flash the merged hex file.
This fixes flashing for samples. Before "west flash" only worked for
tests.
I don't know why this was not done from the get-go.
This also fixes builds that enables CONFIG_TFM_REGRESSION_NS, which will
use the tfm_ns application file instead of the zephyr application, and
will merge tfm_ns hex into the merged hex file. Otherwise the wrong
application hex file will be flashed.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
A FEM in this case is an external Front-End Module. This is basically
a range booster with some extra amplification in the TX and RX paths.
This feature is supported for the Nordic open source controller. See
the changes to the ubx_bmd345eval_nrf52840 board for a quick summary
of what you have to do to take advantage of this.
(This patch doesn't actually remove the feature in the openisa HAL,
though, because that never implemented the required GPIO handling
routines.)
We are using the 'fem' property previously added to the
nordic,nrf-radio's devicetree binding, which points to the FEM that is
in use. If you have this property and the node it points to is
enabled, the controller subsystem respects it. Otherwise, FEM support
is disabled.
This obsoletes the following Kconfig options, which are now unused:
- CONFIG_BT_CTLR_GPIO_PA
- CONFIG_BT_CTLR_GPIO_PA_PIN
- CONFIG_BT_CTLR_GPIO_PA_POL_INV
- CONFIG_BT_CTLR_GPIO_PA_OFFSET
- CONFIG_BT_CTLR_GPIO_LNA
- CONFIG_BT_CTLR_GPIO_LNA_PIN
- CONFIG_BT_CTLR_GPIO_LNA_POL_INV
- CONFIG_BT_CTLR_GPIO_LNA_OFFSET
- CONFIG_BT_CTLR_FEM_NRF21540
- CONFIG_BT_CTLR_GPIO_PDN_PIN
- CONFIG_BT_CTLR_GPIO_PDN_POL_INV
- CONFIG_BT_CTLR_GPIO_CSN_PIN
- CONFIG_BT_CTLR_GPIO_CSN_POL_INV
- CONFIG_BT_CTLR_GPIO_PDN_CSN_OFFSET
The PA and LNA pins are now specified via fem-specific devicetree
properties in the FEM node:
- The "generic" PA/LNA case is handled with the ctx-gpios and
crx-gpios properties of the generic-fem-two-ctrl-pins compatible,
respectively.
- If the fem is an nRF21540, use the tx-en-gpios and rx-en-gpios
properties instead (and also respectively). This allows us to specify
FEM properties in a way that makes sense for the hardware datasheet,
while still handling them in a uniform way within the controller.
We support this in the nRF5 HAL with a new radio_nrf5_fem.h
sub-header, which pulls in radio_nrf5_fem_generic.h or
radio_nrf5_fem_nrf21540.h depending on the fem node's compatible, if
one is defined. These in turn let us replace the implementation
routines in radio.c with DT equivalents.
Keep in-tree users and devicetree binding documentation up to date.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Disable CAN bus tests since can1 is disabled by default due to an IRQ
conflict with the USB controller.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Rename the Zephyr chosen property for specifying the default CAN bus
controller from "zephyr,can-primary" to "zephyr,canbus".
The "zephyr,can-primary" property name was selected in antipation of
adding support for redundant CAN networks, which we have yet to
add. Meanwhile, the "primary" term causes confusion for non-redundant
CAN bus configurations (and the "can" term doesn't match the name of the
Zephyr CAN bus subsystem).
The CAN in Automation (CiA) 302-6, which deals with CANopen network
redundancy, uses the terms "default interface" and "redundant
interface". If/when we add support for redundant CAN networks, the
"zephyr,canbus" chosen property can be supplemented with a
"zephyr,canbus-redundant" chosen property.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Arduino Nano 33 board has undefined I2C_0 and I2C_1
configs. This removes it as I2C_TWIN kconfig already
handles it by its DTS file.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This commit enables the USB OTG full-speed instance (OTG)
on the target board b_u585i_iot02a from STMicroelectronics.
OTG is available on USB type-C connector (CN1).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Enable watchdog timer on RT1160 evk. This was tested using
the watchdog timer api test (tests/drivers/watchdog/wdt_basic_api)
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
