pcie: add PCIe Controller API
This adds a generic PCIe Controller driver API providing the necessary callbacks & config structure to handle the PCIe config space and BAR regions handling. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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Neil Armstrong
Carles Cufí
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3f68124c56
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c714368691
1 changed files with 294 additions and 0 deletions
294
include/drivers/pcie/controller.h
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294
include/drivers/pcie/controller.h
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/**
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* @file
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*
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* @brief Public APIs for the PCIe Controllers drivers.
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*/
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/*
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* Copyright (c) 2021 BayLibre, SAS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DRIVERS_PCIE_CONTROLLERS_H_
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#define ZEPHYR_INCLUDE_DRIVERS_PCIE_CONTROLLERS_H_
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#include <zephyr/types.h>
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#include <device.h>
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/**
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* @brief PCI Express Controller Interface
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* @defgroup pcie_controller_interface PCI Express Controller Interface
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* @ingroup io_interfaces
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* @{
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Function called to read a 32-bit word from an endpoint's configuration space.
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*
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* Read a 32-bit word from an endpoint's configuration space with the PCI Express Controller
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* configuration space access method (I/O port, memory mapped or custom method)
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*
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* @param dev PCI Express Controller device pointer
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* @param bdf PCI(e) endpoint
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* @param reg the configuration word index (not address)
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* @return the word read (0xFFFFFFFFU if nonexistent endpoint or word)
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*/
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typedef uint32_t (*pcie_ctrl_conf_read_t)(const struct device *dev, pcie_bdf_t bdf,
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unsigned int reg);
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/**
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* @brief Function called to write a 32-bit word to an endpoint's configuration space.
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*
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* Write a 32-bit word to an endpoint's configuration space with the PCI Express Controller
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* configuration space access method (I/O port, memory mapped or custom method)
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*
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* @param dev PCI Express Controller device pointer
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* @param bdf PCI(e) endpoint
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* @param reg the configuration word index (not address)
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* @param data the value to write
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*/
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typedef void (*pcie_ctrl_conf_write_t)(const struct device *dev, pcie_bdf_t bdf,
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unsigned int reg, uint32_t data);
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/**
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* @brief Function called to allocate a memory region subset for an endpoint Base Address Register.
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*
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* When enumerating PCIe Endpoints, Type0 endpoints can require up to 6 memory zones
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* via the Base Address Registers from I/O or Memory types.
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*
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* This call allocates such zone in the PCI Express Controller memory regions if
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* such region is available and space is still available.
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*
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* @param dev PCI Express Controller device pointer
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* @param bdf PCI(e) endpoint
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* @param mem True if the BAR is of memory type
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* @param mem64 True if the BAR is of 64bit memory type
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* @param bar_size Size in bytes of the Base Address Register as returned by HW
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* @param bar_bus_addr bus-centric address allocated to be written in the BAR register
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* @return True if allocation was possible, False if allocation failed
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*/
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typedef bool (*pcie_ctrl_region_allocate_t)(const struct device *dev, pcie_bdf_t bdf,
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bool mem, bool mem64, size_t bar_size,
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uintptr_t *bar_bus_addr);
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/**
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* @brief Function called to translate an endpoint Base Address Register bus-centric address
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* into Physical address.
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*
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* When enumerating PCIe Endpoints, Type0 endpoints can require up to 6 memory zones
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* via the Base Address Registers from I/O or Memory types.
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*
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* The bus-centric address set in this BAR register is not necessarely accessible from the CPU,
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* thus must be translated by using the PCI Express Controller memory regions translation
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* ranges to permit mapping from the CPU.
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*
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* @param dev PCI Express Controller device pointer
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* @param bdf PCI(e) endpoint
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* @param mem True if the BAR is of memory type
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* @param mem64 True if the BAR is of 64bit memory type
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* @param bar_bus_addr bus-centric address written in the BAR register
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* @param bar_addr CPU-centric address translated from the bus-centric address
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* @return True if translation was possible, False if translation failed
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*/
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typedef bool (*pcie_ctrl_region_xlate_t)(const struct device *dev, pcie_bdf_t bdf,
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bool mem, bool mem64, uintptr_t bar_bus_addr,
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uintptr_t *bar_addr);
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/**
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* @brief Read a 32-bit word from a Memory-Mapped endpoint's configuration space.
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*
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* Read a 32-bit word from an endpoint's configuration space from a Memory-Mapped
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* configuration space access method, known as PCI Control Access Method (CAM) or
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* PCIe Extended Control Access Method (ECAM).
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*
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* @param cfg_addr Logical address of Memory-Mapped configuration space
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* @param bdf PCI(e) endpoint
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* @param reg the configuration word index (not address)
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* @return the word read (0xFFFFFFFFU if nonexistent endpoint or word)
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*/
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uint32_t generic_pcie_ctrl_conf_read(mm_reg_t cfg_addr, pcie_bdf_t bdf, unsigned int reg);
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/**
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* @brief Write a 32-bit word to a Memory-Mapped endpoint's configuration space.
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*
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* Write a 32-bit word to an endpoint's configuration space from a Memory-Mapped
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* configuration space access method, known as PCI Control Access Method (CAM) or
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* PCIe Extended Control Access Method (ECAM).
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*
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* @param cfg_addr Logical address of Memory-Mapped configuration space
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* @param bdf PCI(e) endpoint
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* @param reg the configuration word index (not address)
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* @param data the value to write
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*/
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void generic_pcie_ctrl_conf_write(mm_reg_t cfg_addr, pcie_bdf_t bdf,
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unsigned int reg, uint32_t data);
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/**
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* @brief Start PCIe Endpoints enumeration.
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*
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* Start a PCIe Endpoints enumeration from a Bus number.
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* When on non-x86 architecture or when firmware didn't setup the PCIe Bus hierarchy,
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* the PCIe bus complex must be enumerated to setup the Endpoints Base Address Registers.
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*
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* @param dev PCI Express Controller device pointer
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* @param bdf_start PCI(e) start endpoint (only bus & dev are used to start enumeration)
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*/
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void generic_pcie_ctrl_enumerate(const struct device *dev, pcie_bdf_t bdf_start);
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/** @brief Structure providing callbacks to be implemented for devices
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* that supports the PCI Express Controller API
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*/
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__subsystem struct pcie_ctrl_driver_api {
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pcie_ctrl_conf_read_t conf_read;
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pcie_ctrl_conf_write_t conf_write;
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pcie_ctrl_region_allocate_t region_allocate;
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pcie_ctrl_region_xlate_t region_xlate;
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};
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/**
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* @brief Read a 32-bit word from an endpoint's configuration space.
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*
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* Read a 32-bit word from an endpoint's configuration space with the PCI Express Controller
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* configuration space access method (I/O port, memory mapped or custom method)
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*
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* @param dev PCI Express Controller device pointer
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* @param bdf PCI(e) endpoint
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* @param reg the configuration word index (not address)
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* @return the word read (0xFFFFFFFFU if nonexistent endpoint or word)
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*/
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static inline uint32_t pcie_ctrl_conf_read(const struct device *dev, pcie_bdf_t bdf,
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unsigned int reg)
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{
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const struct pcie_ctrl_driver_api *api =
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(const struct pcie_ctrl_driver_api *)dev->api;
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return api->conf_read(dev, bdf, reg);
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}
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/**
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* @brief Write a 32-bit word to an endpoint's configuration space.
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*
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* Write a 32-bit word to an endpoint's configuration space with the PCI Express Controller
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* configuration space access method (I/O port, memory mapped or custom method)
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*
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* @param dev PCI Express Controller device pointer
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* @param bdf PCI(e) endpoint
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* @param reg the configuration word index (not address)
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* @param data the value to write
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*/
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static inline void pcie_ctrl_conf_write(const struct device *dev, pcie_bdf_t bdf,
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unsigned int reg, uint32_t data)
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{
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const struct pcie_ctrl_driver_api *api =
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(const struct pcie_ctrl_driver_api *)dev->api;
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api->conf_write(dev, bdf, reg, data);
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}
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/**
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* @brief Allocate a memory region subset for an endpoint Base Address Register.
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*
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* When enumerating PCIe Endpoints, Type0 endpoints can require up to 6 memory zones
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* via the Base Address Registers from I/O or Memory types.
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*
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* This call allocates such zone in the PCI Express Controller memory regions if
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* such region is available and space is still available.
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*
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* @param dev PCI Express Controller device pointer
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* @param bdf PCI(e) endpoint
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* @param mem True if the BAR is of memory type
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* @param mem64 True if the BAR is of 64bit memory type
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* @param bar_size Size in bytes of the Base Address Register as returned by HW
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* @param bar_bus_addr bus-centric address allocated to be written in the BAR register
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* @return True if allocation was possible, False if allocation failed
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*/
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static inline bool pcie_ctrl_region_allocate(const struct device *dev, pcie_bdf_t bdf,
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bool mem, bool mem64, size_t bar_size,
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uintptr_t *bar_bus_addr)
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{
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const struct pcie_ctrl_driver_api *api =
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(const struct pcie_ctrl_driver_api *)dev->api;
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return api->region_allocate(dev, bdf, mem, mem64, bar_size, bar_bus_addr);
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}
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/**
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* @brief Translate an endpoint Base Address Register bus-centric address into Physical address.
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*
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* When enumerating PCIe Endpoints, Type0 endpoints can require up to 6 memory zones
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* via the Base Address Registers from I/O or Memory types.
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*
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* The bus-centric address set in this BAR register is not necessarely accessible from the CPU,
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* thus must be translated by using the PCI Express Controller memory regions translation
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* ranges to permit mapping from the CPU.
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*
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* @param dev PCI Express Controller device pointer
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* @param bdf PCI(e) endpoint
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* @param mem True if the BAR is of memory type
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* @param mem64 True if the BAR is of 64bit memory type
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* @param bar_bus_addr bus-centric address written in the BAR register
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* @param bar_addr CPU-centric address translated from the bus-centric address
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* @return True if translation was possible, False if translation failed
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*/
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static inline bool pcie_ctrl_region_xlate(const struct device *dev, pcie_bdf_t bdf,
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bool mem, bool mem64, uintptr_t bar_bus_addr,
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uintptr_t *bar_addr)
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{
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const struct pcie_ctrl_driver_api *api =
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(const struct pcie_ctrl_driver_api *)dev->api;
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if (!api->region_xlate) {
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*bar_addr = bar_bus_addr;
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return true;
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} else {
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return api->region_xlate(dev, bdf, mem, mem64, bar_bus_addr, bar_addr);
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}
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}
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/** @brief Structure describing a device that supports the PCI Express Controller API
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*/
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struct pcie_ctrl_config {
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/* Configuration space physical address */
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uintptr_t cfg_addr;
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/* Configuration space physical size */
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size_t cfg_size;
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/* BAR regions translation ranges count */
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size_t ranges_count;
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/* BAR regions translation ranges table */
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struct {
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/* Flags as defined in the PCI Bus Binding to IEEE Std 1275-1994 */
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uint32_t flags;
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/* bus-centric offset from the start of the region */
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uintptr_t pcie_bus_addr;
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/* CPU-centric offset from the start of the region */
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uintptr_t host_map_addr;
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/* region size */
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size_t map_length;
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} ranges[];
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};
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/*
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* Fills the pcie_ctrl_config.ranges table from DT
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*/
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#define PCIE_RANGE_FORMAT(node_id, idx) \
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{ \
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.flags = DT_RANGES_CHILD_BUS_FLAGS_BY_IDX(node_id, idx), \
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.pcie_bus_addr = DT_RANGES_CHILD_BUS_ADDRESS_BY_IDX(node_id, idx), \
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.host_map_addr = DT_RANGES_PARENT_BUS_ADDRESS_BY_IDX(node_id, idx), \
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.map_length = DT_RANGES_LENGTH_BY_IDX(node_id, idx), \
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},
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#ifdef __cplusplus
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}
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#endif
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/**
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* @}
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*/
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#endif /* ZEPHYR_INCLUDE_DRIVERS_PCIE_CONTROLLERS_H_ */
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