Make the LSE driving capability configurable for the STM32 series.
Fixes#44737.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Introduce a set_up_pll configuration function and make PLL configuration
an elementary step of the whole system clock configuration.
To implement this new, function make use of the existing series specific
files which allows series specific configuration when required.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add STM32_FOO_ENABLED and STM32_FOO_FREQ to STM32 fixed clocks:
HSI, HSE, MSI(S), CSI, LSI, LSE..
Replace STM32_LSE_CLOCK by STM32_LSE_FREQ and when possible
replace by new STM32_LSE_ENABLED when making sense.
Fix STM32_PLL3_FOO_ENABLE to STM32_PLL3_FOO_ENABLED
Additionally, add STM32_PLL_FOO_ENABLED definitions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Enable PWR clock unconditionally for L4, L5 and U5
like it is done on other stm32 series
Fixes#37781
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
To allow transition to device tree based clock configuration on
stm32 targets, rework clock_control driver to use intermediate
STM32_ macros initially defined as the equivalent Kconfig macros
for now.
Propagate the change in all code using these macros.
The reason to introduce these new macros instead of configuring
Kconfig flags using dt kconfigfunctions is that we'll need
to be able to inform users that Kconfig flags are deprecated
once the whole family conversion is done, to encourage
out of tree users to adopt this new configuration scheme.
Note: For now STM32H7 series and code is excluded.
This is the same for some series specific code such as
PLL mul/div for L0/L1 and XTRE prescaler on F1 series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
