86469b1d0b
Make the LSE driving capability configurable for the STM32 series. Fixes #44737. Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
104 lines
2.4 KiB
C
104 lines
2.4 KiB
C
/*
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*
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* Copyright (c) 2017 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <stm32_ll_bus.h>
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#include <stm32_ll_pwr.h>
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#include <stm32_ll_rcc.h>
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#include <stm32_ll_utils.h>
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#include <drivers/clock_control.h>
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#include <sys/util.h>
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#include <drivers/clock_control/stm32_clock_control.h>
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#include "clock_stm32_ll_common.h"
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#include "stm32_hsem.h"
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#if STM32_SYSCLK_SRC_PLL
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/* Macros to fill up division factors values */
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#define z_pllm(v) LL_RCC_PLLM_DIV_ ## v
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#define pllm(v) z_pllm(v)
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#define z_pllr(v) LL_RCC_PLLR_DIV_ ## v
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#define pllr(v) z_pllr(v)
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/**
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* @brief Set up pll configuration
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*/
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int config_pll_sysclock(void)
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{
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uint32_t pll_source, pll_m, pll_n, pll_r;
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#ifdef PWR_CR5_R1MODE
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/* set power boost mode for sys clock greater than 80MHz */
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if (sys_clock_hw_cycles_per_sec() >= MHZ(80)) {
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LL_PWR_EnableRange1BoostMode();
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}
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#endif /* PWR_CR5_R1MODE */
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pll_n = STM32_PLL_N_MULTIPLIER;
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pll_m = pllm(STM32_PLL_M_DIVISOR);
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pll_r = pllr(STM32_PLL_R_DIVISOR);
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/* Configure PLL source */
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if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
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pll_source = LL_RCC_PLLSOURCE_HSI;
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} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
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pll_source = LL_RCC_PLLSOURCE_HSE;
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} else if (IS_ENABLED(STM32_PLL_SRC_MSI)) {
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pll_source = LL_RCC_PLLSOURCE_MSI;
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} else {
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return -ENOTSUP;
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}
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LL_RCC_PLL_ConfigDomain_SYS(pll_source, pll_m, pll_n, pll_r);
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LL_RCC_PLL_EnableDomain_SYS();
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return 0;
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}
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#endif /* STM32_SYSCLK_SRC_PLL */
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/**
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* @brief Activate default clocks
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*/
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void config_enable_default_clocks(void)
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{
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#ifdef LL_APB1_GRP1_PERIPH_PWR
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/* Enable the power interface clock */
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
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#endif
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#if STM32_LSE_ENABLED
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/* LSE belongs to the back-up domain, enable access.*/
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#if defined(CONFIG_SOC_SERIES_STM32WBX)
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/* HW semaphore Clock enable */
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LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_HSEM);
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#endif
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z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
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/* Set the DBP bit in the Power control register 1 (PWR_CR1) */
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LL_PWR_EnableBkUpAccess();
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while (!LL_PWR_IsEnabledBkUpAccess()) {
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/* Wait for Backup domain access */
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}
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/* Configure driving capability */
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LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR_LSEDRV_Pos);
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/* Enable LSE Oscillator (32.768 kHz) */
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LL_RCC_LSE_Enable();
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while (!LL_RCC_LSE_IsReady()) {
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/* Wait for LSE ready */
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}
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LL_PWR_DisableBkUpAccess();
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z_stm32_hsem_unlock(CFG_HW_RCC_SEMID);
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#endif
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}
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