Provide proper adaptions as bootloader ROM offset, flash load
offset and dts definitions for the nRF54H20 iron board to make it
ready for the MCUBoot bootloader.
Signed-off-by: Michal Kozikowski <michal.kozikowski@nordicsemi.no>
In the default configuration, cv32a6 does not have an FPU and does not
implement RISC-V's F and D extensions.
Hence, the FPU flags should not be added.
In the future, a second SoC for cv32a6 systems with FPU can be added.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
The nullpointer address (0x0) is mapped to the debug module in cva6,
making it a valid address.
Thus, in the coredump test, trigger an exception using k_panic()
instead.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
The original commit uses the incorrect value 42 for
CONFIG_MAX_IRQ_PER_AGGREGATOR for the cva6 family of SoCs,
which is the total number of IRQs in the system.
This commit corrects this to 30, the number of IRQs for the PLIC.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
This commit adds the necessary configurations for building and testing
cva6 boards (cv64a6_genesys_2, cv32a6_genesys_2) with twister.
This has been validated against commit
8a9d7a832b7121dd6f9be61a380d1d89ebf2a5f3 of the cva6 hardware project.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
In hardware, cva6 currently only provides global disable/enable
functions for the Dcache and Icache. Disabling and re-enabling them also
has the effect of flushing and invalidating the cache.
Future cva6 SoCs will add support RISC-V's standardized cache management
operations.
This commit provides a default implementation for all methods currently
part of the cache API. These implementations can be overwritten at board
or SoC level, as they use weak linking.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
The device tree entry for cva6 is currently missing a device tree node
for the mtime and mtimecmp registers in the core-local interrupt
controllers.
This causes the RISC-V machine timer driver not to be built, causing
build failures as the system clock is missing.
This commit rectifies this by adding the corresponding device tree
entry.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
`pthread_setspecific` requires a stack in order to allocate the
`struct pthread_key_data` data structure. On 64 bit systems this data
structure is 32 bytes, resulting in 160 bytes usage for the default 5
supported threads.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Don't `imply POSIX_MESSAGE_PASSING` when `POSIX_API=y` as this option
has a non-trivial RAM implication in `HEAP_MEM_POOL_ADD_SIZE_MQUEUE`.
The `mq_*` API is minimally used in-tree, with all users already
enabling the symbol directly.
Signed-off-by: Jordan Yates <jordan@embeint.com>
The required jlink script was not added due to missing entry in the
board check. Also change the check for app vs rad to be on SOC level.
Signed-off-by: Håkon Amundsen <haakon.amundsen@nordicsemi.no>
- Sets MAIN_STACK_SIZE in prj.conf to 2048 (default is 1024)
to avoid possible stack overflow
and adding new .conf files per board.
- Deletes existing board .conf files, as they are not needed anymore.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
The flash size is the second part (size) of the first reg value, not the
first part (address) of a nonexistent second reg value.
Based-on-patch-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Extend timeout on k_mem_slab_alloc() for kernel.memory_slabs
memory_slab_1cpu.mslab test suite as a workaround to allow its run
on slow platforms, e.g. simulated intel_ish_5_8_0.
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
For enterprise mode we need to install multiple certs to the TLS
credentials store, so, add a helper script in python to make it work
cross-platforms.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
This commit fixes all includes in testlib according to IWYU rules and
sorts all includes in ascending order by name.
Signed-off-by: Aleksander Wasaznik <aleksander.wasaznik@nordicsemi.no>
This commit adds an option to verify weather the host has read the value
after the wire 3-0 bits have been updated.
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
When compiling with C++ enabled (CONFIG_CPP), add an unused member to
prevent an empty struct; this makes the struct size the same for both C
and C++.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
As the sample uses VLAN which needs Ethernet support make sure
CONFIG_NET_L2_ETHERNET is set in prj.conf file.
Signed-off-by: Jukka Rissanen <jukka.rissanen@nordicsemi.no>
Commit 6a2cbc7c87 ("boards: nrf53*: add L|HFXO configurations") missed
the fix for nRF7002DK which is also based on nRF53 SoC.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
Signed-off-by: Aleksandar Stanoev <aleksandar.stanoev@nordicsemi.no>
Refactored stepper move_to calls and move_by calls.
Now, relative movement required or absolute target position
is calculated and then redirected to move_by or move_to calls
respectively.
Signed-off-by: Dipak Shetty <shetty.dipak@gmx.com>
Added missing includes and fixed typos in the header files
for Bluetooth.
There is one exception in hci_vs.h where `struct arch_esf`
is still missing an include, but that is because that
is only specific for ARM.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
Use power state pointers instead of copies which improves performance.
Align power_mgmt_multicore test which was creating pm states in
runtime.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
In I3C v1.0, there was a RSTDAA direct CCC. It is deprecated in I3C v1.1
and later. This adds a CCC helper for it.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
This adds a v1.0 support dts flag for devices. This also makes it so it
doesn't try to send a GETCAPS (GETHDRCAP) ccc if this flag is set and it
doesn't support any HDR modes.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Bluetooth had two public types with similar name _bt_gatt_ccc and
bt_gatt_ccc, but for absolutely different purposes.
That caused misunderstanding of relationship of them and cases
where to use which one.
Commit changes name of _bt_gatt_ccc to more suitable by usage and
improves documentation of it.
Additionally, it changes name of BT_GATT_CCC_INITIALIZER
to correspond the type name.
Signed-off-by: Aleksandr Khromykh <aleksandr.khromykh@nordicsemi.no>
If something is tagged as nocache it didn't got cleared, which could
lead some weird behaviour where bss memory is non-zero.
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
The current configuration allocate 476kB (672 − 196) to the NWP. This
configuration is only required with offloaded network stack
(CONFIG_WIFI_SILABS_SIWX91X_NET_STACK_OFFLOAD).
Since this parameter is not set by default, increase memory allocated to
Zephyr.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Chip siwx91x has 672kB of SRAM shared between the Cortex-M4 (Zephyr) and
the NWP (Network Processor). 3 memory configurations are possible for
the Cortex-M4:
- 196kB
- 256kB
- 320kB
Less memory is allocated to Zephyr, more memory is allocated to NWP,
better are the WiFi and BLE performances.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Some instances of DMA (dma0) can use the normal sram to store their
descriptors. In this case, it makes sense to allow the linker to
allocate the memory rather than tweaking the memory layout.
So, if the attribute silabs,sram-region is not defined, use a statically
allocated buffer.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
