DMA can be initialized with the other devices. The user only need to the
ensure CONFIG_DMA_INIT_PRIORITY is less than the DMA consumers.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Memory areas for DMA descriptors are shared with the DMA hardware block.
There area should be cached by the CPU.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Silabs siwx91x hardware use specific memory areas to store descriptors
for DMA requests. These areas are tightly coupled between the CPU and
the hardware. This helps in reducing the wait cycles.
Until now these addresses was also hard coded in the DT and in the
linker script. This patch leverage the zephyr,memory-region driver to
centralize the information in the DT.
Then, with this new implementation, the memory mapping is easier to
understand for the reader.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Add more tests cases to the AF_PACKET sockets test suite, covering the
summary of the packet socket functionalities prepared from various
sources (mostly man pages).
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Make sure that when sendto is being used without the socket being bound
before, a correct interface is used for transmission. As
zpacket_sendto_ctx() calls net_context_recv() to register receive
callback before sending, a default binding was used by the context
layer, which would bind the socket to the default interface. This could
lead to unexpected results, i.e. packet being sent on a default
interface, even though a different one was specified.
Make also sure that there is no ambiguity in the interface selection -
the application should be explicitly clear what interface it wants to
use when it comes to packet sockets. It's better to return an error if
no valid interface was specified.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
According to AF_PACKET man pages protocol number 0 is allowed, however
in such case the socket is only capable of transmitting packets then:
"If protocol is set to zero, no packets are received."
Therefore, allow to create sockets with such protocol, and at the
connection.c level filter out such sockets from data reception.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
The test case did not do what it said, it was supposed to receive data
on both RAW and DGRAM packet sockets, but instead it received on RAW
socket twice.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Test interface configuration doesn't change throught the test suite
execution, therefore there's no need to reiterate the interfaces to set
the interface pointers in each test case. Do it just once, when test
suite is setup.
Also remove the __test_packet_sockets() function which seemed no longer
useful with all those simplifications.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Packet socket tests used non-blocking sockets so in results the test
code was overly complicated with delays and loops scattered all across
the test code, making it difficult to read.
As packet sockets do support blocking operation with timeout,
reconfigure the sockets to use that and simplify the test code by
getting rid of unnecessary loops and delays.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Test suite prints a warning on boot about not enough IPv4 context
instances compared to the number of interfaces, therefore adjust the
config value to get rid of it.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Make sure all sockets used in test are closed even in case of test
failure. Otherwise, a single test failure could derail other tests,
making the results obfuscated.
Remove redundant code related to socket creation.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Add link check support, by adding:
- link check callback in response of LinkCheckAns.
- link check request function using LinkCheckReq.
Signed-off-by: Martin Durietz <martin.durietz@gmail.com>
The command should work with existing certs rather than a generic
example, also fix the key-management.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
RSA3K based certs are not supported on all platforms, so, keep both
variants, rsa2k (the older certs but with longer expiry 9999 days) and
rsa3k (latest ones) and we can have more variants in this folders.
Also, add a cmake variable to override the path with default as rsa3k.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
Certificates usage depends on STA/AP mode, but we don't have that
information at a build time, so, make all certs as optional and if a
file isn't found then generate an empty header so that corresponding C
code will be built.
Any missing mandatory certificates will be validated before connection
and connection is failed.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
Deletion of credential should use the pointer from the reference slot
not the temporary buffer, this causes a crash (unknown error).
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
Instead of having an overlay move the Enterprise configurations to a
dedicated snippet so that it can be enabled with any sample.
Can be used along with Wi-Fi snippet e.g., `-S
"wifi-ipv4;wifi-enterprise"`.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
The volatile backend stores the credentials on the heap, so, explicitly
add a config option that can be overridden in case there are more certs
than the default.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
Using TLS credentials library add support for run-time certificates where
the installed certs are retrieved from the credential store (as of now
only volatile backend is tested).
This helps in production environments.
Implements #79564.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
The console can't input when waken up from PM3, as get the wrong
usart_intenset when process PM_DEVICE_ACTION_TURN_ON and the
USART interrupt is not enabled. Only saving usart_intenset after
PM action of PM_DEVICE_ACTION_TURN_OFF can fix this issue.
Signed-off-by: Maochen Wang <maochen.wang@nxp.com>
Replace the manually implemented GPIO-based I2C recovery logic
with Zephyr's i2c_bitbang API.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The npcx4 SoC only uses 86 NVIC IRQ numbers.
This commit updates the number from 128 to 86 to reduce the memory
usage.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
The signedness of the variable caused undefined behavior because the
sign bit is modified when it gets left-shifted.
This fixes that by changing it to an unsigned variable.
Signed-off-by: Daniel Hajjar <daniel.hajjar16@gmail.com>
I3C can contain a lot of features that may be unused. Add Kconfigs for
enabling controller and/or target code. Choosing just one can reduce
the code size footprint.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Adjusted the VW change check timings:
- Polling time changed from 100 uSec to 1 uSec.
- Timeout value changed from 10 mSec to 1 mSec.
This is to achieve the lowest possible pulse width for SCI VW in S0,
while ensuring that the VW change check is still reliable for S0iX
where SoC may take longer to process upstream events.
Also added -ETIMEDOUT error when failure.
Signed-off-by: Aditya Bhutada <aditya.bhutada@intel.com>
When looking for jump address in the syscall table, we need to
multiply the syscall ID by 4 before adding the address offset
of the beginning of the table. This is due to the jump address
being 32-bit (4 bytes). Instead of using two instructions to
shift the ID by 4 first and then the addition, we can use one
ADDX4 instruction to achieve the same result.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Since the necessary register values are now pre-computed and
stored in the memory domain struct, we can use them directly
in various assembly locations, thus replacing the function
call to xtensa_swap_update_page_tables().
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Create alias for struct k_mem_domain into k_mem_domain_t,
and struct _mem_domain_info into _mem_domain_info_t via
typedef. These are needed to generate offsets via
GEN_OFFSET_SYM.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When context switching and dealing with non-nested interrupts,
the context to be restored are saved in the thread stack.
When userspace is enabled, this means saving context into
the user stacks for user threads. This allows PS values to be
manipulated externally by setting PS.RING in the saved PS
value to 0, resulting in granting kernel access privilege when
the thread is restored. To prevent this, we store the PS value
into the thread struct instead, where user threads cannot
manipulate that. Note that nested interrupts and syscalls are
not using the user stack but the interrupt stack and thread
privileged stack respectively, where they are not accessible
under user mode.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When syscall assembly is executed, the EPC points to the syscall
instruction, and we have to manually advance it so we will
return to the instruction after syscall to continue execution.
However, with zero-overhead loops and the syscall instruction is
the last instruction, this simple addition does not work as it
would point past the loop and would have skipped the loop.
Because of this, syscall entrance would need to look at the loop
registers and set the PC back to the beginning of loop if we are
still looping. Assuming most of the syscalls are not inside
loops, the extra handling code consumes quite a few cycles.
To workaround this, simply adds a nop after syscall so we no
longer have to deal with loops at syscall entrance, and that
a nop is faster than all the code to manipulate loop registers.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This extends arch_cohere_stacks() to handle privileged stacks of
user threads when userspace is enabled.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Towards the end of interrupt handling, and before restoring
context, we would spill all register windows. This requires
A0 and A1 to be restored from the saved context so spilling
would work correct. However, when coherence is enabled,
window spilling has already been done earlier so there is
no need to spill the register windows again. So there is
no need to restore A0 and A1. They will be restored again
before returning from interrupt anyway.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Instead of computing all the needed register values when
swapping page tables, we can pre-compute those values when
the memory domain is first initialized. Should save some
time during context switching.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There is no need for ZSR_FLUSH when threads are pin only
(CONFIG_SCHED_CPU_MASK_PIN_ONLY=y), so there is no need to
reserve it.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
In xtensa_userspace_enter, we were hard-coding to use level 2
interrupt return mechanism to pivot to user mode and start
running the user thread. However, EPC2 and EPS2 may be used
for other purposes, and they could be used for interrupt
return if there are only two level interrupts. So change
the userspace enter to use ZSR_RFI_LEVEL, ZSR_EPC and ZSR_EPS
instead to be more explicit.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When returning from syscall, we cannot use RFE by using EPC1.
As there is no EPS1, we would need to write to PS before
returning. However, this creates a situation where interrupts
are being enabled (since PS is set), and any interrupts will
overwrite EPC1 before we return (which ensures chaos as we
would be returning to the wrong address). So utilize the same
mechanism as interrupt returning by use ZSR_EPS, ZSR_EPC and
ZSR_RFI_LEVEL.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There is no need to do a jump to _syscall_returned as it is
the next to be run anyway. Keep the label there so we can
set breakpoint if needed.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
We stuff the 7th argument into stack by moving the stack pointer
before calling syscall handler. The Xtensa ABI says stack must
be 16-byte aligned. So instead of moving stack pointer 4 bytes,
we move 16 bytes (assuming stack has been aligned so far).
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Xtensa ISA mentions that stack always needs to be aligned on
16 bytes. So we need to pad the stack frame to be also 16 bytes
aligned when dealing with interrupts. Or else the stack would
not be 16 bytes aligned when we add the stack frame to stack
during interrupt handling.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When crossing stack during interrupt handling, we do two call4
to pivot to the interrupt stack, with arguments to these two
call4 stashed in A6, A10 and A11. However, A4-A11 may be marked
as invalid in the register file, and accessing them would
result in window overflowing. At that point, A0 and A1 are not
setup to handle window overflows, and will result in registers
being stashed in incorrect location, resulting in incorrect
value being restored during window underflowing. So move around
the code a bit to restore A0 and A1 properly before accessing
A4-A11.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Do not force CONFIG_XTENSA_SMALL_VECTOR_TABLE_ENTRY when MMU
is enabled. It is up to the SoC to decide whether they need
this.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The logic to swap page tables or MPU entries is moved to the end
of cross stack call, since it is still running in the interrupt
stack instead of the thread stack. The old logic was calling
the swap functions in the outgoing thread stack, which is not
desirable.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When switching page table and MPU enties, we need to call
corresponding functions via call4 which would move the register
window. So we need to do that earlier before we start saving
context into stack by manipulating stack pointer manually which
definitely would interfere with window spilling.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
During arch_cohere_stacks(), the used portion of the outgoing
thread is cache flushed, and then the unused portion of cache
invalidated. However, this results in the cache line at
the stack pointer being flushed and then invalidated due to
how sys_cache_data_*() operates. If we are swapping back to
the same thread (e.g. after handling interrupt), this cache
line will need to be retrieved again from main memory since
it has already been invalidated. This creates unnecessary
data move between cache and main memory. So create our own
version of cache flushing and invalidation routines just for
arch_cohere_stacks(). Bouns is that these work directly with
bounding addresses and skips the size calculation which should
save a little bit amount of execution time.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This removes _xstack_call1_* trampoline as we can simply use
callx4 to jump to the interrupt handler.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
