Re-running the script that checks for the const qualifier missing on
struct device ISR's parameter.
The script also changes the parameter 'arg' to 'dev' when relevant.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
- Move SWJ_CFG initialization into pinmux.
- Don't disable the AFIO clock after SWJ_CFG
initialization.
- Apply '111' to the SWJ_CFG bits upon remap
application, that fixes the remap usage.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
- Move SWJ_CFG initialization into pinctrl.
- Don't disable the AFIO clock after SWJ_CFG
initialization.
- Apply '111' to the SWJ_CFG bits upon remap
application, that fixes the remap usage.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
The Serial Wire JTAG configuration is moved to
F1 pinctrl DTS.
The configuration in GPIO didn't apply to the
majority of the STM MCUs except F1.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Use the Kconfig macros of MODEM_GSM_RX_STACK_SIZE and
MODEM_GSM_WORKQ_STACK_SIZE directly without another macros.
They are well within the column limit and this make them
more obvious that they are actually configurable by Kconfig.
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
The driver should check for cellular registration before
attempting to attach to packet service, otherwise it will just
fails.
This patch waits for registration for 300 seconds, configurable
by CONFIG_MODEM_GSM_REGISTER_TIMEOUT, if it isn't registered by
then, it would toggle the airplane mode using AT+CFUN & wait
again, until it is registered, or `gsm_ppp_stop` is invoked.
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Back with commit a1b77fd589 huge chunk of code was automatically
refactored using a script, which in turn left some macros meaningless
Signed-off-by: Hristo Mitrev <hr.mitrev@gmail.com>
Just use dev->name. This change follow same principles applied when
DEV_CFG and DEV_DATA macros were removed.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Move the can_set_bitrate() function to can_common.c as it is getting
quite long for a static inline function.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add support for getting the maximum supported bitrate in bits/s for CAN
controller/transceiver combination and check that a requested bitrate is
within the supported range.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add support for the new pinctrl API to the nRF PWM driver.
Update code of the driver and the related devicetree binding.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for the new pinctrl API to the nRF QDEC driver.
Update code of the driver and the related devicetree binding.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for the new pinctrl API to the nRF QSPI NOR flash driver.
Update code of the driver and the related devicetree binding.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for configuring pins to be used by the nRF PWM, QDEC, and
QSPI peripherals.
A new custom property "nordic,invert" is added to the pin configuration
group binding to allow configuring PWM channel outputs as inverted.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for the new pinctrl API to the DMIC driver that handles
the nRF PDM peripheral. Update code of the driver and the related
devicetree binding.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for the new pinctrl API to the nRF I2S driver. Update code
of the driver and the related devicetree binding.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
I introduced some errors during the gpio_dt_spec/i2c_dt_spec conversion
process. This patch fixes the issues so that driver builds.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Driver implementation for the Xilinx Processor System MIO / EMIO GPIO
controller as contained in the Zynq-7000 and ZynqMP (UltraScale) SoCs.
The driver is split up into source and header for a parent controller
device and source and header for 1..n child GPIO pin bank devices.
The parent device driver takes care of IRQ handling, the GPIO pin bank
driver provides pin / bank access according to the API defined by the
GPIO subsystem.
More than one device for this type of GPIO controller is required as
it provides access to a number of GPIO pins well in excess of the 32
pins addressable by the current GPIO API (whereever parameters or
return values come in the form of a bit mask):
- Zynq-7000: 54 MIO GPIO pins, 64 EMIO GPIO pins in 4 banks.
- ZynqMP: 78 MIO GPIO pins, 96 EMIO GPIO pins in 6 banks.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
Use the devicetree properties to determine if the dedicated temperature or
voltage reference channels should be configured for the ADC.
Fixes#43750.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
The stm32's I2C peripheral has a maximum transmission size. Larger trans-
action, that I2C itself allows, can be achieved be using the peripheral's
reload-mode.
In order to do that, st's low-lever drivers need to be informed according-
ly. The previous iteration of the code mishandled the next_msg_flags para-
meter, causing the issue to manifest itself.
This refactors the inner loop of i2c_stm32_transfer() into its own func-
tion. This passes the message parameter by value in order to be able to
mutate its state while keeping the original datum from the user intact
during the entire procedure.
Fixes#43235
Signed-off-by: Frank Terbeck <ft@bewatermyfriend.org>
Claim the net_context mutext associated with a socket before claiming
the socket mutex. The receive callback claims the net_context mutex
internally, which will now always succeed immediately.
The TX path claims the net_context mutex before the socket mutex, and if
we don't use the same order, we can end up in a deadlock.
Fixes#43470.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
It may happen that after the flash chip was previously put into
the Deep Power Down mode, the system was reset but the flash chip
was not. Consequently, the flash chip can be in the DPD mode when
the QSPI driver is initialized. Some flash chips will just exit
the DPD mode on the first CS pulse, but some need to receive the
dedicated command to do it and they will not respond to any other
commands including those that the driver need to perform to complete
its initialization ("Read status register" and "Read JEDEC ID").
This commit adds sending of the "Release from Deep Power Down"
command right after initialization of the QSPI interface to avoid
the problem described above.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Previous commit 579ca90e25 to
build wifi drivers as a library changed the include path for
the WINC1500 driver, which results in the include path being
local to the library. However, the Atmel HAL requires
wifi_winc1500_nm_bsp_internal.h to in the search path. So
change the include path to be global.
Fixes#43456
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Refactors the remaining I2S drivers to use the shared driver class
initialization priority configuration, CONFIG_I2S_INIT_PRIORITY, to
allow configuring I2S drivers separately from other devices. This is
similar to other driver classes.
The default is set to CONFIG_KERNEL_INIT_PRIORITY_DEVICE to be
consistent with other driver classes.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Fix register bit field when clock source is MSI
on the stm32L0x or stm32L1x mcus
Use RCC_CR_MSIRGSEL bit field instead of not soc stm32wbx serie
That bit of the RCC CR is common to several stm32 mcus
Signed-off-by: Francois Ramu <francois.ramu@st.com>
After experiencing a few deadlocks, it was discovered that this bus does
not implement any form of mutual exclusion... this patch addresses this
and resolves potential deadlocks.
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
Refactors interrupt controller drivers to use the shared driver class
initialization priority configuration, CONFIG_INTC_INIT_PRIORITY, to
allow configuring interrupt controller drivers separately from other
devices. This is similar to other driver classes.
The default is set to CONFIG_KERNEL_INIT_PRIORITY_DEFAULT to preserve
the existing default initialization priority for most drivers.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Refactors the remaining I2C drivers to use the shared driver class
initialization priority configuration, CONFIG_I2C_INIT_PRIORITY, to
allow configuring I2C drivers separately from other devices. This is
similar to other driver classes.
The default is set to CONFIG_KERNEL_INIT_PRIORITY_DEVICE to preserve the
existing default initialization priority for most drivers.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Enable second usb EHCI if usb2 node has status="okay" Note that this
driver is still an single instance driver, this change simply enables
the driver to work with the usb2 peripheral if that one is enabled, and
usb1 is disabled.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This change includes special handling of the internal voltage
reference and internal die temperature channels for all currently
defined STM32 models
The code now looks for specific ADC + channel ID pairs instead
of just a channel ID to determine if the caller is trying to
configure an internal channel.
Signed-off-by: Pete Dietl <petedietl@gmail.com>
