This file started using ALWAYS_INLINE from <toolchain.h> but didn't
include it. Transitive inclusions were hiding the problem most
places, but at least one test case exposes it.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
These are tiny functions always declared as "inline" per C99, but
that's just a hint. In practice, they tend to be (c.f. intel_asdp)
called from very early boot circumstances where main application
symbols aren't yet available. That obviously doesn't work, or even
link.
Make them ALWAYS_INLINE. In practice they're so small that we don't
want them called anyway just for stack space reasons.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
As memory region names are now derived purely from devicetree, remove
the `name` parameter from `DT_REGION_FROM_NODE_STATUS_OKAY`. Name is
`zephyr,linker-region` if it exists, otherwise the node path.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
This adds basic support for GDB stub on Xtensa. Note that
this only provides the common bits on the architecture side.
SoC support is also required to fully enable GDB stub on
each Xtensa SoC.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds some architecture-specific functions to read/write
registers for the GDB stub. This is in preparation for the actual
introduction of these functions in the core GDB stub code to
avoid breaking the build in between commits.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The RISC-V architecture linker script was including `cplusplus-ram.ld`
linker script before `__data_region_start`, and this caused the content
of `.gcc_except_table` section to be not copied to the RAM by the
`z_data_copy` function; leading to the C++ exception handling
malfunction.
This commit relocates the `cplusplus-ram.ld` linker script inclusion
such that the contents of the relevant sections are properly copied by
the `z_data_copy` function.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This change adds `k_cycle_get_64()` on platforms that
support a 64-bit cycle counter.
The interface functions `arch_k_cycle_get_64()` and
`sys_clock_cycle_get_64()` are also introduced.
Fixes#39934
Signed-off-by: Christopher Friedt <chrisfriedt@gmail.com>
This commit adds Xen hypervisor call interface for arm64 architecture.
This is needed for further development of Xen features in Zephyr.
Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
Add the inclusion of the Common Peripheral Access Layer for aarch32
Cortex-A SoCs in combination with the respective SoC's header file,
in which the feature flags evaluated in core_ca.h must be provided.
The corresponding CMSIS include path is added to the build by setting
the HAS_CMSIS_CORE_A Kconfig item for all aarch32 Cortex-A CPUs.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@Weidmueller.com>
Introduce support for On-Chip Memory (OCM) areas in aarch32 Cortex-A
SoCs. This memory area is suitable for, amongst other things, un-
cached device DMA. The OCM memory can reside either at address zero
or at a high memory address, with configuration of the memory's lo-
cation similar to the configuration of the location of the exception
vectors. In both cases, it must be assured that the low/high OCM
area declaration doesn't overlap with the exception vectors memory
page at either the low/high address. Therefore, all possible OCM
location options shall be described in the SoC's device tree, the
current location shall be indicated via a "chosen" entry in the
target board's device tree.
This commit contains the necessary changes to the linker-related
files as well as the static region declaration for the MMU in-
itialization in the Zynq-7000 SoC-specific init code.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
Modification of the ARM architected timer driver and its configuration
data in order to address an erratum which exists at least in the Cor-
tex-A9 CPU, and which can also be observed in the QEMU implementation
of the Cortex-A9.
Comp.: ARM Cortex-A9 processors Software Developer Errata Notice
ARM document ID032315
Erratum 740657
This erratum causes a spurious interrupt pending indication with the
interrupt controller if no new compare value is written within the
timer ISR before the interrupt is cleared. This is usually the case
in tickless mode. If the spurious interrupt is not prevented, the
timer ISR will be called twice, but on second execution, the pending
flag is not set within the timer's register space. Not handling this
issue will lead to erratic tick announcements to the kernel.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
Modify #ifdefs so that any code that is compiled if CONFIG_ARMV7_R is
set is also compiled if CONFIG_ARMV7_A is set.
Modify #ifdefs so that any code that is compiled if CONFIG_CPU_CORTEX_R
is set is also compiled if CONFIG_CPU_AARCH32_CORTEX_A is set.
Modify source dir inclusion in CMakeLists.txt accordingly.
Brief file descriptions have been updated to include Cortex-A whereever
only Cortex-M and Cortex-R were mentioned so far.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
An initial implementation for memory management using the ARMv7 MMU.
A single L1 translation table for the whole 4 GB address space is al-
ways present, a configurable number of L2 page tables are linked to
the L1 table based on the static memory area configuration at boot
time, or whenever arch_mem_map/arch_mem_unmap are called at run-time.
Currently, a CPU with the Multiprocessor Extensions and execution at
PL1 are always assumed. Userspace-related features or thread stack
guard pages are not yet supported. Neither are LPAE, PXN or TEX re-
mapping. All mappings are currently assigned to the same domain. Re-
garding the permissions model, access permissions are specified using
the AP[2:1] model rather than the older AP[2:0] model, which, accor-
ding to ARM's documentation, is deprecated and should no longer be
used. The newer model adds some complexity when it comes to mapping
pages as unaccessible (the AP[2:1] model doesn't support explicit
specification of "no R, no W" permissions, it's always at least "RO"),
this is accomplished by invalidating the ID bits of the respective
page's PTE.
Includes sources, Kconfig integration, adjusted CMakeLists and the
modified linker command file (proper section alignment!).
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
_ARCH_MEM_PARTITION_ALIGN_CHECK was missing for arc mpu v3 and v6.
This commit add the missing macros.
Signed-off-by: Yuguo Zou <yuguo.zou@synopsys.com>
BUILD_ASSERT macro was disabled for MWDT toolchain from the
moment of adding MWDT support to Zephyr. Built-in _Static_assert
is now working fine for the most of the cases with MWDT toolchain
so we can use it in BUILD_ASSERT.
The only exception is _ARCH_MEM_PARTITION_ALIGN_CHECK macro
as it often used with variable addresses as parameters
which need to be checked at compile time. We disable
_ARCH_MEM_PARTITION_ALIGN_CHECK for MWDT toolchain so we can use
BUILD_ASSERT in other places.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Don't allow to enable multiple register banks / fast
interrupts if we have only one interrupt priority level.
NOTE: we duplicate some checks by adding dependencies to ARC
Kconfig and adding build-time checks in C code. We do it
intentionally as for some reason we can violate dependencies
in architecture-level Kconfig by adding incorrect default in
SoC-level Kconfig. Such violation happens without any
warnings / errors from the Kconfig.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Add new common inline functions sys_set_bits and set_clear_bits to set
and clear multiple bits via bit mask in single function call.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
On non-XIP system, RAM region overlaps ROM region which cause PMP region
overlapping. Padding RAM region by adding a output section to update
the next free address of RAM region.
Signed-off-by: Jim Shu <cwshu@andestech.com>
In non-XIP system, because ROMABLE_REGION == RAMABLE_REGION, setting
__rom_region_size/end symbol at linker script end will mistakely
contain RAMABLE_REGION in it.
Move __rom_region_end symbol to end of common ROMABLE_REGION (text
and rodata) instead in non-XIP system.
Signed-off-by: Jim Shu <cwshu@andestech.com>
When _app_smem region is empty, alignment is also needed. If there
is no alignment, the _app_smem_start used by arm mpu can be lower
than __rodata_region_end, and this two regions can overlap.
The Armv8-R aarch64 MPU does not allow overlapped regions.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Fix the attrs of init fix mem regions for userspace.
Allow RAM region and RO region be read-only for EL0.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Add a new macro MEM_DOMAIN_ALIGN_AND_SIZE for mmu and mpu mem
alignment.
MEM_DOMAIN_ALIGN_AND_SIZE is
- CONFIG_MMU_PAGE_SIZE, when mmu is enabled.
- CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE when mpu enabled.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Include the new introduced include/arch/arm64/mm.h instead of the
arm_mmu.h or arm_mpu.h.
Unify function names z_arm64_thread_pt_init/z_arm64_swap_ptables with
z_arm64_thread_mem_domains_init/z_arm64_swap_mem_domains for mmu and
mpu, because:
1. mmu and mpu have almost the same logic.
2. mpu doesn't have ptables.
3. using the function names help reducing "#if define" macros.
Similarly, change z_arm64_ptable_ipi to z_arm64_domain_sync_ipi
And fix a log bug in arm_mmu.c.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
The defination of K_MEM_PARTITION_* marcos denpens on wheather it is
mmu or mpu, so I move those definations for mmu into arm_mmu.h and
create mpu relevant ones in arm_mpu.h
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
The arm_mmu.h and arm_mpu.h have some common logic. To reduce some
redundency and the ugly 'if defined' marcos, I add a new header
include/arch/arm64/mm.h to include arm_mmu.h or arm_mpu.h depending on
CONFIG_ARM_MMU or CONFIG_ARM_MPU. Thus, in the future, the common code
of mmu and mpu should be in include/arch/arm64/mm.h.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
This patch mainly moves mpu related code from
arch/arm64/core/cortex_r/mpu/ to arch/arm64/core/cortex_r/ and moves
the mpu header files from include/arch/arm64/cortex_r/mpu/ to
include/arch/arm64/cortex_r/
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Fixes: #38591, #38207, #37861
The commit 65a2de84a9 aligned the data
linker symbol for sections and regions.
The data region symbol start has been placed outside the sections thus
being defined as the address of the region before alignment of the first
section in the data region, usually the `datas` section.
The symbol defining the start address of the data section is after
section alignment.
In most cases the address of the data region start and datas section
start will be identical, but not always.
The data region symbol is a new linker symbol and existing code has
been depending on the old data section start symbol.
Thus, the update to the use of the data region start symbol instead of
data ram start symbol thus results in a different address when the
section is aligned to a different address.
To ensure the original behavior in all cases, the data region start
address is now moved inside the data section.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Currently we are using mxcsr register with the bit 6 DAZ enabled.
When the denormals-are-zeros flag is set, the processor
converts all denormal source operands to a zero with the sign
of the original operand before performing any computations on them.
It causes bugs in the SIMD XMM registers computation like #38646
I suggest to disable Denormals-Are-Zeros flag and mask division-by-zero
exception.
Set value to the default 1F80H according to the Intel(R) 64 and IA-32
Architectures Software Developer's Manual.
Fix will let all x86 boards perform SIMD computation using XMM
registers in the correct way.
Fixes#38646
Signed-off-by: Maksim Masalski <maksim.masalski@intel.com>
__cxa_atexit implementation provided by MWDT startup code calls
malloc which isn't supported right now. As we don't support
calling static destructors in Zephyr let's provide our own
__cxa_atexit stub and get rid of MWDT startup libs
entirely.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Cleanup and preparation commit for linker script generator.
Zephyr linker scripts provides start and end symbols for each section,
and sometimes even size and LMA start symbols.
Generally, start and end symbols uses the following pattern, as:
Section name: foo
Section start symbol: __foo_start
Section end symbol: __foo_end
However, this pattern is not followed consistently.
To allow for linker script generation and ensure consistent naming of
symbols then the following pattern is introduced consistently to allow
for cleaner linker script generation.
Section name: foo
Section start symbol: __foo_start
Section end symbol: __foo_end
Section size symbol: __foo_size
Section LMA start symbol: __foo_load_start
This commit aligns the symbols for __itcm_load_start and
__dtcm_data_load_start to other symbols and in such a way they follow
consistent pattern which allows for linker script and scatter file
generation.
The symbols are named according to the section name they describe.
Section names are itcm and dtcm.
The following symbols are aligned in this commit:
- __itcm_rom_start -> __itcm_load_start
- __dtcm_data_rom_start -> __dtcm_data_load_start
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Cleanup and preparation commit for linker script generator.
Zephyr linker scripts provides start and end symbols for each larger
areas in the linker script.
The symbols _image_text_start and _image_text_end sometimes includes
linker/kobject-text.ld. This mean there must be both the regular
__text_start and __text_end symbols for the pure text section, as well
as <group>_start and <group>_end symbols.
The symbols describing the text region which covers more than just the
text section itself will thus be changed to:
_image_text_start -> __text_region_start
_image_text_end -> __text_region_end
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Cleanup and preparation commit for linker script generator.
Zephyr linker scripts provides start and end symbols for each larger
areas in the linker script.
The symbols _image_rom_start and _image_rom_end corresponds to the group
ROMABLE_REGION defined in the ld linker scripts.
The symbols _image_rodata_start and _image_rodata_end is not placed as
independent group but covers common-rom.ld, thread-local-storage.ld,
kobject-rom.ld and snippets-rodata.ld.
This commit align those names and prepares for generation of groups in
linker scripts.
The symbols describing the ROMABLE_REGION will be renamed to:
_image_rom_start -> __rom_region_start
_image_rom_end -> __rom_region_end
The rodata will also use the group symbol notation as:
_image_rodata_start -> __rodata_region_start
_image_rodata_end -> __rodata_region_end
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Cleanup and preparation commit for linker script generator.
Zephyr linker scripts provides start and end symbols for each section,
and sometimes even size and LMA start symbols.
Generally, start and end symbols uses the following pattern, as:
Section name: foo
Section start symbol: __foo_start
Section end symbol: __foo_end
However, this pattern is not followed consistently.
To allow for linker script generation and ensure consistent naming of
symbols then the following pattern is introduced consistently to allow
for cleaner linker script generation.
Section name: foo
Section start symbol: __foo_start
Section end symbol: __foo_end
Section size symbol: __foo_size
Section LMA start symbol: __foo_load_start
This commit aligns the symbols for _data_ram/rom to other symbols and in
such a way they follow consistent pattern which allows for linker script
and scatter file generation.
The symbols are named according to the section name they describe.
Section name is `data`
A new group named data_region is introduced which instead spans all the
input and output sections that was previously covered by
__data_ram_start, __data_ram_end, and __data_rom_start.
The following symbols are aligned in this commit:
- __data_ram_start -> __data_region_start
- __data_ram_end -> __data_region_end
- __data_rom_start -> __data_region_load_start
The following new symbols are introduced so that the data section is
aligned with other sections:
- __data_end
- __data_start
value identical to __data_region_start but describes start of
the section.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Commit 6b3c5e8bb2 removed the use of
_DATA_IN_ROM but kept the now unused define.
This commit removes the corresponding define which is no longer used.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Add support of ARC mpu v6
* minimal region size down to 32 bytes
* maximal region number up to 32
* not support uncacheable region and volatile uncached region
* clean up mpu code for better readablity
Signed-off-by: Yuguo Zou <yuguo.zou@synopsys.com>
Both arch_k_cycle_get_32() and z_tsc_read() are marked inline.
However, compiler may decide not to inline them which would put
them in the generic text section. Pin them in physical memory
as they are frequently used functions to avoid page fault costs.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Although they are marked as an inline functions, the compiler
may decide not to inline them which would result in them being
outside the pinned text section. Since these functions are
required for userspace to work correctly, pin them in physical
memory.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Move the IDT_LIST memory region to the location recommended by
`intlist.ld`. The documentation specifies that this region should not
overlap other regions, and there is no guarantee that the area after the
`SRAM` region is not used. The end of the address space is much less
likely to be a valid RAM address.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
As of today we have libraries provided by MWDT build with
stackcheck enabled. So we have to provide dummy
_fstack, _estack to make it working.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Enable RISC-V GP relative addressing by linker relaxation to reduce
the code size. It optimizes addressing of globals in small data section
(.sdata).
The gp initialization at program start needs each SoC support. Also,
if RISC-V SoC has custom linker script, SoC should provide
__global_pointer$ symbol in it's linker script.
Signed-off-by: Jim Shu <cwshu@andestech.com>
RISC-V global pointer (GP) register is neither caller nor callee
register, and it's a constant value in the single ELF file. Thus, we
don't need to save/restore GP at ISR enter/exit. Remove it to optimize
context switch performance.
Signed-off-by: Jim Shu <cwshu@andestech.com>
