Commit graph

5481 commits

Author SHA1 Message Date
Jimmy Zheng
f216c434d0 soc: gd32: gd32vf103: keep the mcause.interrupt by SOC-specific context
For Nuclei ECLIC, the interrupt level (mintstatus.MIL) is restored from
the previous interrupt level (mcause.MPIL) only if mcause.interrupt is set.
This behavior is not defined in the RISC-V CLIC spec.
If an ISR causes a context switch and mcause.interrupt is not set in the
next context (e.g. the next context is yielded from ecall), interrupts will
be masked after MRET because the interrupt level is not restored.

Use SOC-specific context to set mcause.interrupt to ensure the interrupt
level is restored correctly.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2025-02-05 17:48:45 +01:00
Bjarki Arge Andreasen
7e0e583f9e soc: nordic: nrf54h: gpd: yield() to not block if main is coop
The main thread, if configured with coop priority (don't do that :D)
breaks gpd since it has a non yielding while loop (also don't do that)

Add an explicit yield() to allow other threads to run if main or other
threads use gpd with coop prio.

Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
2025-02-05 12:25:10 +01:00
Declan Snyder
b83f8ed070 soc: nxp: Make clock init weak and global
Make clock init functions in SOC level weak and global so they can be
overriden by board/app level.

Ideally these should have been put at board level but for now just make
them weak so they can be overriden without breaking anything.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2025-02-05 10:20:41 +01:00
Vebjorn Myklebust
9d81b74ff1 drivers: pinctrl: Add support for cc23x0 pinctrl
Add support for pinctrl to cc23x0 SoC. Like for other TI SoCs,
a node approach is implemented (no grouping approach).

Signed-off-by: Lars Thalian Morstad <l-morstad@ti.com>
Signed-off-by: Vebjorn Myklebust <v.myklebust@ti.com>
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
Signed-off-by: Julien Panis <jpanis@baylibre.com>
2025-02-04 11:56:05 +01:00
Vebjorn Myklebust
1a7e89cb21 soc: ti: Add support for new SoC cc23x0
Datasheet: https://www.ti.com/lit/ds/symlink/cc2340r5.pdf
TRM: https://www.ti.com/lit/ug/swcu193/swcu193.pdf

Signed-off-by: Lars Thalian Morstad <l-morstad@ti.com>
Signed-off-by: Vebjorn Myklebust <v.myklebust@ti.com>
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
Signed-off-by: Julien Panis <jpanis@baylibre.com>
2025-02-04 11:56:05 +01:00
Aksel Skauge Mellbye
e2660e50d6 soc: silabs: Distinguish Gecko SDK from SiSDK HAL
When the SiSDK HAL was introduced, a corresponding Kconfig option
was not. Update Series 2 SoCs to use the new option.

Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
2025-02-04 09:19:53 +01:00
Emilio Benavente
97200b04ad soc: nxp: mcx: Add MCXW72
Add MCXW72 SOC, SOC Kconfigs, and
Platform Init code

Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
2025-02-04 09:17:04 +01:00
Erwan Gouriou
3d04068393 soc: stm32n6: Generate a warning when signing tool is not available
Generate a proper Cmake warning when signing tool isn't available.
This also allows not to fail in Github CI.


Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2025-02-03 19:56:49 +01:00
Erwan Gouriou
3c097d8662 soc: stm32n6: Add Boot serial option
This option should be used to load and run binary using "serial boot"
configuration for boot ROM.

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2025-02-03 19:56:49 +01:00
McAtee Maxwell
55ec415793 soc: modifications for cyw920829m2evk_02 mpu regions
- Modifcation to mpu information, in relation to functionality
	  in userspace

Signed-off-by: McAtee Maxwell <maxwell.mcatee@infineon.com>
2025-02-03 19:50:11 +01:00
Tran Van Quy
5c81b70442 soc: renesas: ra: Add SoC support for Renesas RA4M1
Add support for Renesas RA4M1 SoC series with r7fa4m1ab3cfp

Signed-off-by: Tran Van Quy <quy.tran.pz@renesas.com>
2025-02-03 14:01:59 +01:00
Christian Galante
dd7547420b soc: silabs: add configuration to enable acmp module
The ACMP module is enabled with this change in the gecko
and simplicity_sdk hal libraries for development on silabs
devices. This is a pre-requisite for implementing the
comparator driver that is compatible with silabs acmp
peripherals.

Signed-off-by: Christian Galante <christian.galante@silabs.com>
2025-02-03 11:16:57 +01:00
Gediminas Sidlauskas
88c7a443f9 soc: nxp: imxrt: fixed relocated file name
Added .c ending to lpm_rt1064 file name.

Signed-off-by: Gediminas Sidlauskas <gediminas.sidlauskas@gmail.com>
2025-01-31 21:43:25 +01:00
Felix Schramek
9f2f4a4256 soc: add FlexSPI2 clock configuration in clock_init for rt11xx
The current soc clock_init only configures the FlexSPI1 interface and
not the FlexSPI2.

This Commit adds the clock configuration for the second FlexSPI
in case one boots from the FlexSPI2.

Signed-off-by: Felix Schramek <felix.schramek@gmail.com>
2025-01-31 21:42:56 +01:00
Mahesh Mahadevan
4e31be313a soc: nxp_rw: Update pinctrl setting for FlexSPI
The FSEL bit for FlexSPI should not be cleared as part of
configuring the FlexSPI pins.

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2025-01-30 20:28:20 +01:00
Aksel Skauge Mellbye
120691a155 drivers: pinctrl: silabs: Add support for analog bus allocation
The GPIO peripheral on Silabs Series 2 devices is responsible for
allocating analog buses to analog peripherals. Enable support for
this in the pinctrl driver. Since these bus allocations are not
digital pins, introduce a new property silabs,analog-bus for this
purpose.

Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
2025-01-30 18:30:01 +01:00
Mahesh Mahadevan
85bdab00de soc: mimxrt1180: Add USB support
This was tested on the MIMXRT1180 EVK board

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2025-01-30 18:29:33 +01:00
Nikodem Kastelik
c61a5178fe soc: nordic: nrf53: kconfig: mark RAM CTRL as supported
nRF5340 SoC supports nrfx RAM control helper.

Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
2025-01-30 16:21:30 +01:00
Nikodem Kastelik
8b495dc316 soc: nordic: poweroff: remove disabling of emul l05/l10 unused RAM
Code is now incorporated into SystemInit() function of MDK 8.69.1,
which is integrated within nrfx 3.10.0.

Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
2025-01-30 16:21:30 +01:00
Marcio Ribeiro
c3b53d0fa3 soc: esp32xx: makes esp_console_init() calling conditional
Makes the esp_console_init() calling during hardware initialization
conditioned to CONFIG_ESP_CONSOLE

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2025-01-30 16:21:13 +01:00
Maureen Helm
398d9e3d49 soc: adi: max32: Enable primary core to configure/start secondary core
Adds support for the primary m4 core to configure the boot address and
start the clock for the secondary risc-v core. Unlike the msdk which
defers this function to applications and requires users to copy/paste
code from an msdk example application into their own application, in
zephyr it is implemented in the common soc init routine of the primary
core. It can be enabled/disabled and configured with Kconfig symbols and
a devicetree chosen node, allowing applications to override board-level
defaults if desired using overlays instead of modifying zephyr code.

Signed-off-by: Maureen Helm <maureen.helm@analog.com>
2025-01-29 17:55:32 +01:00
Maureen Helm
466a322f14 soc: adi: max32: Refactor core configuration
Refactors the max32 soc family configuration to allow socs with cores
other than arm cortex-m4. This will make it possible to add support for
the secondary risc-v core that exists on some max32 variants.

Signed-off-by: Maureen Helm <maureen.helm@analog.com>
2025-01-29 17:55:32 +01:00
Marcin Szymczyk
cb4b350700 soc: nordic: vpr: fix CLOCK_CONTROL default value
VPR cores should not enable this option.

Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
2025-01-28 18:16:38 +01:00
Marcin Szymczyk
16e4af4f6d soc: nordic: vpr: enable GP relative addressing
`RISCV_GP` will now be used to reduce code size and speed up
execution.

Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
2025-01-28 18:16:38 +01:00
Marcin Szymczyk
0b52052a19 soc: nordic: vpr: use SystemInit() as soc_reset_hook
Similarly to ARM cores, VPRs should call `SystemInit()`
at reset.

Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
2025-01-28 18:16:38 +01:00
Marcin Szymczyk
d7525cd500 soc: riscv_privileged: support soc_reset_hook
Add call to `soc_reset_hook` if `CONFIG_SOC_RESET_HOOK` is enabled.

Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
2025-01-28 18:16:38 +01:00
Guillaume Gautier
25dea79d4c soc: st: stm32: stm32n6x: add signing tool
Generate signed binary necessary to start a program from Flash on STM32N6

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2025-01-28 18:14:45 +01:00
Guillaume Gautier
722310e6b1 soc: st: stm32: add a comment for kconfig source priority
Add a comment describing Kconfig source order priority to prevent
future questions (after overriding SYS_CLOCK_HW_CYCLES_PER_SEC config
for STM32N6).

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2025-01-28 18:14:45 +01:00
Guillaume Gautier
016d048ded soc: st: stm32: add stm32n6 series
Add STM32N6 series

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2025-01-28 18:14:45 +01:00
Lucien Zhao
5d87295350 soc: nxp: imxrt: select HAS_MCUX_FLEXCOMM Kconfig
lpi2c driver on RT700 depend on HAS_MCUX_FLEXCOMM

Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
2025-01-28 09:47:32 +01:00
Khoa Nguyen
305ae84457 dts: arm: renesas: ra: Add support for Renesas RA4E1 soc
Add support for r7fa4e10d2cfm, r7fa4e10d2cne soc

Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
2025-01-28 07:57:03 +01:00
Yassine El Aissaoui
b67c0f423d soc: nxp: rw: Fix nxp_nbu_init implicit definition warning
nxp_nbu_init extern definition is under CONFIG_NXP_RW6XX_BOOT_HEADER
and this produces an implicite definition warning when
the Kconfig is disabled. This is the case when both BLE Kconfig
and MCUboot bootloader Kconfig are enabled.

Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
2025-01-28 00:05:31 +01:00
Maximilian Werner
01e511c7f7 soc: mcxc: Set LPUART1 clock source from clock_init
The clock source for LPUART0 for the MCXC family is already
initialized in the corresponding soc.c -> clock_init().
Initialization for LPUART1 is missing. This is however
necessary if a user wants to configure LPUART1 as the default
console output.

Signed-off-by: Maximilian Werner <maximilian.werner96@gmail.com>
2025-01-28 00:05:18 +01:00
Lucien Zhao
1034316a85 soc: nxp: imxrt: imxrt7xx: fix bug pincfg setting missed
A problem was discovered during development: the
electrical characteristics of the pins were not
set according to the device tree settings.

Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
2025-01-27 21:03:26 +01:00
Krzysztof Chruściński
df32919a52 soc: nordic: nrf54l: Set SystemCoreClock using frequency from DT
Use cpu clock source frequency as system core clock.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2025-01-27 17:08:01 +01:00
Jasen Liu
c2df6b0dd1 soc: nxp: rw: fix stack overflow in BLE samples
mbedtls is now used in BLE samples, increasing the stack depth needed
of the calling threads. This was causing stack overflows in several BLE
samples.
Increasing the BT_LONG_WQ_STACK stack size for peripheral_sc_only sample,
 and the SYSTEM_WORKQUEUE stack size for ibeacon sample.

Signed-off-by: Jasen Liu <jasen.liu@nxp.com>
2025-01-27 11:03:05 +01:00
Jasen Liu
f18fed1a0e soc: nxp: mcxw: fix stack overflow in BLE samples
mbedtls is now used in BLE samples, increasing the stack depth needed
of the calling threads. This was causing stack overflows in several BLE
samples.
Increasing the BT_LONG_WQ_STACK stack size for peripheral_sc_only sample,
and the SYSTEM_WORKQUEUE stack size for ibeacon sample.

Signed-off-by: Jasen Liu <jasen.liu@nxp.com>
2025-01-27 11:03:05 +01:00
Ruijia Wang
8c9b226900 mcux: soc: rt1180 unmask reset event when rtwdog is using
RT1180 takes reset event mask feature which should be unmasked when
watch dog is enabled.

Signed-off-by: Ruijia Wang <ruijia.wang@nxp.com>
2025-01-25 20:07:05 +01:00
Andrej Butok
66df94b618 boards: mimxrt1180: fix MCUBoot build
- Fixes building of MCUBoot for mimxrt1180-evk.
- Disables RT Boot header for MCUBoot applications.

Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
2025-01-24 22:09:30 +01:00
Gerson Fernando Budke
0cf7fd1023 drivers: watchdog: atmel: Introduce sam4l wdt
Introduce sam4l watchdog configuration. This entry is necessary to
select proper watchdog configuration at board init due to #83429.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2025-01-24 22:08:29 +01:00
Jiafei Pan
ab25fdf1a9 boards: imx8mp_evk: add i2c support
Added i2c3 support on imx8mp_evk A53 board.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2025-01-24 19:15:57 +01:00
Sreeram Tatapudi
50cdc17aae soc: infineon: cat1b: cyw20829: Enable SOC_EARLY_INIT_HOOK
Power management routine is initialized from the soc_early_init_hook,
but this was not enabled previously.

Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
2025-01-24 01:14:44 +01:00
Adrian Bieri
03fa6a0c33 mcux: drivers: xbara: drop HAS_MCUX_XBARA config
The HAS_MCUX_XBARA is replaced by the DT_HAS_NXP_MCUX_XBAR_ENABLED

Signed-off-by: Adrian Bieri <adrian.bieri@loepfe.com>
2025-01-23 19:25:54 +01:00
Bastien Beauchamp
ec1a2c6f47 soc: silabs: Fix the PRIMASK for Silabs S2 SoCs
sl_power_manager_sleep() doesn't expect the PRIMASK to be set when called.
Setting BASEPRI to 0 was moved to sl_power_manager_is_ok_to_sleep(),
this function is called after sl_power_manager_sleep() has set the PRIMASK.
Added sli_power_manager_on_wakeup() to force a clock restore before the
interrupt are handled. Added a call to retrieve the startup measurements,
reducing the early wakeup time.

Signed-off-by: Bastien Beauchamp <bastien.beauchamp@silabs.com>
2025-01-23 19:23:27 +01:00
Bastien Beauchamp
19756be822 soc: silabs: Fix double WFI for Silabs S2 SoCs
k_cpu_idle() and sl_power_manager_sleep() call WFI.
Remove the call to k_cpu_idle() and add back its tracing and
hook functions.

Signed-off-by: Bastien Beauchamp <bastien.beauchamp@silabs.com>
2025-01-23 19:23:27 +01:00
Bastien Beauchamp
d163d4268e soc: silabs: Fix EM4 enter for Silabs S2 SoCs
Fix PM_STATE_SOFT_OFF to properly enter EM4.

Signed-off-by: Bastien Beauchamp <bastien.beauchamp@silabs.com>
2025-01-23 19:23:27 +01:00
Abderrahmane JARMOUNI
e07896fc9d soc: amd: acp_6_0: Kconfig: fix SOC_TOOLCHAIN_NAME
Add guard for SOC_TOOLCHAIN_NAME symbol default value

Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
2025-01-23 19:22:00 +01:00
Yong Cong Sin
588ccd9698 arch: remove CONFIG_LEGACY_MULTI_LEVEL_TABLE_GENERATION
`CONFIG_LEGACY_MULTI_LEVEL_TABLE_GENERATION` had been deprecated since
#66877 for 2 releases, interrupt controller drivers should have been
updated to use the new `IRQ_PARENT_ENTRY_DEFINE()` macro. Remove it.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
2025-01-23 16:32:36 +01:00
Sylvio Alves
4456ecc0a3 soc: esp32xx: remove unused kconfig entry
ESP_HEAP_SEARCH_ALL_REGIONS kconfig entry is not
used and can be totally removed.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-01-23 13:45:31 +01:00
Xudong Zheng
020cb79d27 drivers: serial: nrfx_uarte: move DEPRECATED_UART_NRFX_UARTE_LEGACY_SHIM
The Kconfig option should be defined alongside
UART_NRFX_UARTE_LEGACY_SHIM for clarity.

Signed-off-by: Xudong Zheng <7pkvm5aw@slicealias.com>
2025-01-23 08:26:33 +01:00