Improve alignment in the source code and limit printed messages
(SYSTEM_CLOCK_NO_WAIT and SYSTEM_CLOCK_WAIT_FOR_* are choice options,
so it is enough to print only the enabled one).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This test needs an initialization step to be done soon after the system
clock is started. ZTEST setup function is too late for that, so use an
initialization function executed at the POST_KERNEL stage instead.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This flag needs to be cleared at the beginning of each test. Otherwise,
when the flag remains set after the previous test, the timer handler is
not rescheduled so executing of the current test is actually pointless.
This was in fact the case with `test_bt_interrupted` before switching
the test suite to the new ZTEST API. When this test was executed as
the second one, the timer handler was called only once and the test
could pass (giving false confirmation that the related routines of
the clock_control_nrf driver work properly). After the API switching,
the order of test execution was changed and that test started failing.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
- most of initialization can be done once per the test suite
(clearing of the iteration counter can be moved to particular
tests where it fits better), so instead of the ZTEST before
function use the setup one for doing the initialization
- make `clock_dev` and `cli` common variables for all tests
- use K_USEC() instead of Z_TIMEOUT_US(), as the latter is an
internal Zephyr macro
- instead of `K_USEC(long_timeout ? 300 : 100)` use `K_USEC(300)`
and `K_USEC(100)` so that their values can be calculated at the
build time
- modify construction of main loops in tests so that it is more
exposed when the `test_end` flag is set
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Remove GPIO toggling, that seems to be remains from some debugging,
as it can potentially interfere with some hardware on specific boards.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Many driver samples or tests only had 'drivers' as the tag, without a
tag indicating what driver that is exactly, so add some missing tags.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
When it needs to access perck clock speed, clock_control driver is using
LL API to read RCC registers and compute frequency.
We're using the exact same method to test the frequency and as a result
we were not able to detect that there was an issue when configuring this
clock.
Add a specific case to this test in order to verify perck domain clock if
perck is used in SPI clk configuration.
We're now able to detect issues (and test is failing).
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Perform some rework in messages displayed in case of failure to ease
readability:
- remove redundant information
- add missing information
- convert registers values to hex
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Test was using "clock-names" property to query domain clock configuration.
This is not working since clock-names was removed in the last step of the
feature implementation and whole macro was always reporting DT_NO_CLOCK.
This issue went undetected because of an additional issue in the exception
case which was testing "zassert_true(1, .." instead of "zassert_true(0, .".
Fix both issues to make the test efficient again.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Change for loops of the form:
for (i = 0; i < CONFIG_MP_NUM_CPUS; i++)
...
to
unsigned int num_cpus = arch_num_cpus();
for (i = 0; i < num_cpus; i++)
...
We do the call outside of the for loop so that it only happens once,
rather than on every iteration.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
test cases in
tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices
are move to new ztest API
Signed-off-by: Meng xianglin <xianglinx.meng@intel.com>
test cases in
tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core
are moved to new ztest API
Signed-off-by: Meng xianglin <xianglinx.meng@intel.com>
test cases in
tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices
are moved to new ztest API
Signed-off-by: Meng xianglin <xianglinx.meng@intel.com>
test cases in
tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core
are moved to new zest API
Signed-off-by: Meng xianglin <xianglinx.meng@intel.com>
test cases in
tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices
are moved to new ztest API
Signed-off-by: Meng xianglin <xianglinx.meng@intel.com>
test cases in
tests/dirvers/clock_control/stm32_clock_configuration/stm32_common_core
are moved to new ztest API
Signed-off-by: Meng xianglin <xianglinx.meng@intel.com>
Many device pointers are initialized at compile and never changed. This
means that the device pointer can be constified (immutable).
Automated using:
```
perl -i -pe 's/const struct device \*(?!const)(.*)= DEVICE/const struct
device *const $1= DEVICE/g' **/*.c
```
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
It is frequent to find variable definitions like this:
```c
static const struct device *dev = DEVICE_DT_GET(...)
```
That is, module level variables that are statically initialized with a
device reference. Such value is, in most cases, never changed meaning
the variable can also be declared as const (immutable). This patch
constifies all such cases.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
On some tests adc node is enabled w/o setting any domain clock.
This is made on purpose but deserves a comment to avoid surprises
for the reader.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In the continuation of the previous commit, replace _OPT_ by _DOMAIN_
in macros relating to this feature.
hen, adapt drivers and tests to this new wording.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add a bunch of missing "zephyr/" prefixes to #include statements in
various test and test framework files.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
In tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices
test suite, core_init.overlay configure msis to use pll-mode.
Since pll-mode is not configured for msik in spi1_msik variant the test
fails since both clocks should support the same configuration regarding
pll mode (an assert in raised in the driver).
Fix this in spi1_msik test variant.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Now that clock control drivers are enabled based on devicetree we
can remove any cases of them getting enabled by *defconfig and
proj.conf files.
Signed-off-by: Kumar Gala <galak@kernel.org>
Instead of enabling WOVCRO clock based on the SOC, use a configuration
to indicate support, so that each platform can specify if WOVCRO is
supported or not.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Intel ADSP CAVS is now a proper series with all CAVS SoCs running under
it. This will give us to Intel ADSP series:
- CAVS
- ACE v1.x
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Any project with Kconfig option CONFIG_LEGACY_INCLUDE_PATH set to n
couldn't be built because some files were missing zephyr/ prefix in
includes
Re-run the migrate_includes.py script to fix all legacy include paths
Signed-off-by: Tomislav Milkovic <milkovic@byte-lab.com>
irq_lock() returns an unsigned integer key.
Generated by spatch using semantic patch
scripts/coccinelle/irq_lock.cocci
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Move to pass 'struct device *' instead of a 'char *'. This lets us move
from device_get_binding to DEVICE_DT_GET.
Signed-off-by: Kumar Gala <galak@kernel.org>
Move to use DEVICE_DT_GET instead of device_get_binding as
we work on phasing out use of DTS 'label' property.
Signed-off-by: Kumar Gala <galak@kernel.org>
Move to use DEVICE_DT_GET instead of device_get_binding as
we work on phasing out use of DTS 'label' property.
Signed-off-by: Kumar Gala <galak@kernel.org>
Move to use DEVICE_DT_GET instead of device_get_binding as
we work on phasing out use of DTS 'label' property.
Signed-off-by: Kumar Gala <galak@kernel.org>
This commit adds a test case that configures an alternative clock source
for an ADC peripheral.
In case no alt clock is available, only the gating clock is enabled
and disabled.
Unlike the i2c and lptim test, the actual gating clock frequency is
not checked, because for the adc there seems to be no uniform way
to retrieve the frequency via the hal.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
For the STM32G0, STM32G4, and STM32WL enable the adc node in one
configuration, and select the PLL_P output as its clock source.
PLL_P divider is chosen to be 20 to make sure it's a unique frequency.
- g0, and g4 have pll as sysclk
- wl has hse as sysclock
The test configurations and the overlay-files are renamed accordingly.
All overlays that don't specify an alternative clock source still
make sure that the adc node is "okay" to be able to perform basic test.
The basic test only turns on and off the gate clock without checking the
frequency.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The test checks if the peripheral gating clock was correctly disabled
after the test, but accidentally the I2C_CLK was checked instead of the
LPTIM_CLK.
This commit fixes this by using __HAL_RCC_LPTIM1_IS_CLK_ENABLED instead.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
