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tests: clock_control: stm32u5 device: Fix clk_msik configuration

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In tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices
test suite, core_init.overlay configure msis to use pll-mode.
Since pll-mode is not configured for msik in spi1_msik variant the test
fails since both clocks should support the same configuration regarding
pll mode (an assert in raised in the driver).

Fix this in spi1_msik test variant.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2022-07-28 16:53:39 +02:00 • committed by Kumar Gala
commit 5fe7b47e52
1 changed files with 1 additions and 0 deletions
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tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/spi1_msik.overlay
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@ -11,6 +11,7 @@
&clk_msik {
msi-range = <4>;
msi-pll-mode;
status = "okay";
};