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tests: drivers: clock_control: stm32: test H7 PLL2_P SPI1

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Tests PLL2_P clock source for the SPI1 (SPI123SEL).

Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
This commit is contained in:
Georgij Cernysiov 2022-11-27 12:12:09 +01:00 • committed by Carles Cufí
commit 7f06af6b82
4 changed files with 41 additions and 0 deletions
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10
tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/core_init.overlay
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@ -47,6 +47,16 @@
status = "disabled";
};
&pll2 {
/delete-property/ div-m;
/delete-property/ mul-n;
/delete-property/ div-p;
/delete-property/ div-q;
/delete-property/ div-r;
/delete-property/ clocks;
status = "disabled";
};
&pll3 {
/delete-property/ div-m;
/delete-property/ mul-n;

25
tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/spi1_pll2p_1.overlay Normal file
View file

@ -0,0 +1,25 @@
/*
* Copyright (c) 2022 Georgij Cernysiov
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after core_init.overlay file.
*/
&pll3 {
clocks = <&clk_hse>;
div-m = <1>;
mul-n = <24>;
div-p = <1>;
status = "okay";
};
&spi1 {
/delete-property/ clocks;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>,
<&rcc STM32_SRC_PLL2_P SPI123_SEL(1)>;
status = "okay";
};

4
tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/src/test_stm32_clock_configuration.c
View file

@ -66,6 +66,10 @@ ZTEST(stm32h7_devices_clocks, test_spi_clk_config)
zassert_equal(spi1_actual_domain_clk, RCC_SPI123CLKSOURCE_PLL,
"Expected SPI src: PLL1 Q (0x%x). Actual: 0x%x",
RCC_SPI123CLKSOURCE_PLL, spi1_actual_domain_clk);
} else if (pclken[1].bus == STM32_SRC_PLL2_P) {
zassert_equal(spi1_actual_domain_clk, RCC_SPI123CLKSOURCE_PLL2,
"Expected SPI src: PLL2 P (0x%x). Actual: 0x%x",
RCC_SPI123CLKSOURCE_PLL2, spi1_actual_domain_clk);
} else if (pclken[1].bus == STM32_SRC_PLL3_P) {
zassert_equal(spi1_actual_domain_clk, RCC_SPI123CLKSOURCE_PLL3,
"Expected SPI src: PLL3 P (0x%x). Actual: 0x%x",

2
tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/testcase.yaml
View file

@ -6,6 +6,8 @@ tests:
extra_args: DTC_OVERLAY_FILE="boards/core_init.overlay;boards/spi1_pllq_1_d1ppre_1.overlay"
drivers.stm32_clock_configuration.h7_dev.spi1_pllq_2_d1ppre_4:
extra_args: DTC_OVERLAY_FILE="boards/core_init.overlay;boards/spi1_pllq_2_d1ppre_4.overlay"
drivers.stm32_clock_configuration.h7_dev.spi1_pll2p_1:
extra_args: DTC_OVERLAY_FILE="boards/core_init.overlay;boards/spi1_pll2p_1.overlay"
drivers.stm32_clock_configuration.h7_dev.spi1_pll3p_1_d1ppre_4:
extra_args: DTC_OVERLAY_FILE="boards/core_init.overlay;boards/spi1_pll3p_1_d1ppre_4.overlay"
drivers.stm32_clock_configuration.h7_dev.spi1_per_ck_d1ppre_1: