Converted over all STM32F1 based boards to use device tree and removed
associated bits that now come from the device tree for STM32F1. Also
renamed the STM32F10{3,7} SoC dtsi to try and make it clear that the 'X'
is a place holder. Fixedup the top level compatiables in the boards to
be the specific 'X' instead of the generic one.
Boards that are now using devicetree:
* Nucleo f103rb
* STM3210C Eval
* STM32 MINI A15
Change-Id: I29b3634ec7451f974687d55980414efa655e2e96
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move back to getting the number of IRQs from Kconfig. We do this
because the number of IRQs should really just be determined by scanning
the device tree and figuring out the highest IRQ value used.
Change-Id: I8e0dbec1d9d036d4e899b237c4dc7d833c422e18
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This patch adds the necessary changes to enable use of DTS for
generating required build information.
Change-Id: I0d7aa15488339a425ffe57b6354992851212f7f3
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Cube HAL implements timeout based on 1ms tick.
This commit allows Cube HAL to get Zephyr system clock.
Change-Id: I9a59edcf6fa8e0ebfd5040348db537dadd9fcdfa
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
A number of SoCs clear out the Mem/Bus/Usage and Hard Fault exceptions
during init. Lets refactor that into a common function so we don't have
to keep duplicating it over and over.
Change-Id: Ida908a9092db37447abcf3c9872f36937982f729
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
It is called before early SoC initialization, so remove the duplicated
code from other boards and just set it by default when using XIP.
This can later be used when adding bootloader support, as an
additional option could be created to move the VTOR offset to a
different address.
Change-Id: Ia1f5d9a066de61858ee287215cefdd58596b6b1c
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.
Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.
Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file. Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.
Jira: ZEP-1457
Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This patch provides initial support for the SoC STM32F107. This SoC
belongs to the Connectivity Line devices.
Connectivity line family incorporates up to 14 communication
interfaces such as: 2 x I2C, 5 x USART, 3 x SPI, 2 x CAN, USB 2.0,
10/100 Ethernet MAC.
Change-Id: I5cb2c458bce9ec1558b4168e87a7003ad9f606a5
Signed-off-by: Adam Podogrocki <adam.podogrocki@rndity.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
replace include <nanokernel.h> with <kernel.h> everywhere and also fix
any remaining mentions of nanokernel.
Keep the legacy samples/tests as is.
Change-Id: Iac48447bd191e83f21a719c69dc26233216d08dc
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Following pinmux update for PWM support,
update soc to support this new configuration.
Change-Id: I1126e347ab1ab6b2d830993e548de8f32fa2f8f9
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Due to new serial driver implementation based on STM32Cube we can
remove the USARTX_ADDR defines as they aren't ended anymore
Change-Id: Icd5b7995429025c5b54b1a04ca6abb9649ab31c8
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32Cube based implementation allows single driver file for
all stm32 based SoCs.
By maximizing code reuse, use of STM32Cube eases new SoCs
porting into Zephyr and provides better maintanability and
maturity.
Change-Id: Ief4b723add3dfc8b2a839683559c5a4c5d5eb837
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This patch fixes the unused parameter warning found at the
arch/arm/core/fault.c and arch/arm/soc/st_stm32/stm32f1/soc_gpio.c
files.
Change-Id: I5b3013c1514cff30f4e98feb31169fb28546c534
Signed-off-by: Flavio Santes <flavio.santes@intel.com>
Make the systick feature optional that can be selected by the SoC.
Change-Id: I4a405640b84daecc17fc1882743d3cafb78ff861
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
PA10 should use *_PA10_UART1_RX
Change-Id: Ifba4d301d049db1d62ea3a63d4d66f75c88a71a6
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
The bitfield determining the I/O direction already defines the pin
as either input or output, cannot be none or both at the same time
This issue was reported by Coverity
Coverity-CID: 151970
Change-Id: I18d5387139d6834004ba3269c5b54176bdc97ea7
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
PRIMARY, SECONDARY, NANOKERNEL, MICROKERNEL init levels are now
deprecated.
New init levels introduced: PRE_KERNEL_1, PRE_KERNEL_2, POST_KERNEL
to replace them.
Most existing code has instances of PRIMARY replaced with PRE_KERNEL_1,
SECONDARY with POST_KERNEL as SECONDARY has had a longstanding bug
where the documentation specified SECONDARY ran before the kernel started
up, but actually ran afterwards.
Change-Id: I771bc634e9caf7f17dbf214a270bc9967eed7d32
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Create HAS_CUBE config flag to control activation of STM32Cube support.
Generate fitting compilation options for STM32Cube in
/ext/hal/stm32cube/Makefile soc.h is updated to include minimum include
files from ext/hal/stm23cube
Change-Id: If58ce0a4fdb7fbf5f171dfe5f1f8eb75126a8313
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In ST CMSIS files, FLASH_BASE does not mean base address of FLASH register
Instead FLASH_R_BASE is used.
stm32f1 clock control driver is updated to be compatible with this naming.
Change-Id: Ic4fb49c60c392e15fd12c69266baf4c686bd343b
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32Cube uses SoC defines made to reflect HW heterogeneity
that should be taken into account by SW.
Aim of this commit is to adapt values used by Zephyr to the same
diversity. This will help create new SoC values only when justified
by a real hardware difference that should be taken into account
by software.
For instance, for SoC stm32f103rb following define is used:
*STM32F103xB
Which means:
*Same SW could be used on STM32F103RB and STM32F103VB:
same CONFIG_SOC could be used
*Different SW should be used on STMF103RB and STM32F103R4:
different CONFIG_SOC should be used
This change focuses on stm32f1xx series.
Change-Id: I5ecfaa52952d04421b27b5e74fb71b4fc108b662
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32F4 requires the alternative function config to be set, so just
initialize that as part of the gpio configure call.
Change-Id: I33a4a8efec59c5ebe7dc3f3580f0dd2bf7ded7f4
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
The STM32F1 range all have the independent watchdog, enable the driver
by default if CONFIG_WATCHDOG is enabled.
Change-Id: I3869884dc51c56194367b46007c87f6cee699689
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Move SRAM_BASE_ADDRESS and FLASH_BASE_ADDRESS to Kconfig.soc since
it will most likely be the same values for all STM32 socs.
Change-Id: I682dc441e34155a19a4f90757707008ef299e9d4
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Moved setting of specific Cortex-M compiler flags in each SoC directory
unify setting them in the arch/arm/soc Makefile.
Add flags for Cortex M0, M0+, M1, M3, M4, and M7. However only
CONFIG_CPU_CORTEX_M3 and CONFIG_CPU_CORTEX_M4 are supported at this time
As part of this change converted Kbuild files for some SoCs into
Makefiles as the Makefiles would be empty otherwise.
Change-Id: Ie4e0178b141ca761ec482a610ae50e94fe58070f
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Introduce a soc-cflags, soc-cxxflags, and soc-aflags as a means for
SoC specific compiler flags to be set without manipulating Kbuild
options directly.
Change-Id: I2c8f5019fb237429e59717ef96bd4251a61dc1a5
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert leading whitespace into tabs in Kconfig files. Also replaced
double spaces between config and <prompt>.
Change-Id: I341c718ecf4143529b477c239bbde88e18f37062
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Avoids confusion with .gitignore rules, which were inadequate to
cover all the places where these files are found. At least in
VIM, these files are now syntax highlighted correctly.
Change-Id: I23810b0ed34129320cc2760e19ed1a610afe039e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The files soc_config.c and soc_gpio.c use errno code so they should
include errno.h.
Change-Id: I94237aa294701cc71ed17ea42eca9d8073d4ae47
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
Use SoC family/series and reoganise the structure to follow new
hierarchy.
Change-Id: I8637f1487a8287a6614ce6636cd018cf342fec95
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Use SOC_SERIES_* for naming SoCs with similar features and architectures
with the goal of code reuse. The Series in the config variable should avoid
name collisions and clearly denote the relationships within an SoC family.
Change-Id: I7a98542f96b5d5dc3acc23782c4d45f98cceb599
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
There is no need to re-define CONFIG_UART_CONSOLE_ON_DEV_NAME to be
"UART_0" all over the place as its default is "UART_0" already.
So remove those duplicate defaults.
Change-Id: Ia86e26b8f90540fdbd7dcb3358d6dac352648b21
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Most of the SoC and board Kconfig use the same values for
driver initialization priorities. So refactor them, and
discard duplicate ones.
The shared IRQ init priority was changed so that the kernel
default init and device init priorities can be standardized
across all SoC/boards. Same goes for DesignWare SPI driver.
This also changes the UART_CONSOLE_PRIORITY and
IPM_CONSOLE_PRIORITY to UART_CONSOLE_INIT_PRIORITY and
IPM_CONSOLE_INIT_PRIORITY, to standardize across all drivers.
Note that this does not take away the ability to override
those values. This just provides reasonable defaults such
that there is virtually no need to override.
Change-Id: Ibbd95d802c637df06f9a2fd48763ee1e6f4ff627
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There are two major issues with the kconfig:
() Some of the config options have incorrect dependencies inside help
under menuconfig. For example, CONFIG_GPIO depends on BOARD_GALILEO.
() Since the SoC and board specific kconfig files are parsed first,
the help screen would say, for example, CONFIG_SPI is defined at
arch/arm/soc/fsl_frdm_k64f/Kconfig. This is incorrect because
the actual config is defined in drivers/spi/Kconfig.
These cause great confusion to users of menuconfig/xconfig.
To fix these, the SoC and board defaults are now to be parsed last.
Note that the position swapping of defaults in this patch is due to
the fact the the default parsed last will be used.
And, spi_test is broken due to the fact that it requires
CONFIG_SPI_INTEL_PORT_1, but never enables it anywhere. This is
bypassed for now.
Origin: refactored and edited from existing files
Change-Id: I2a4b1ae5be4d27e68c960aa47d91ef350f2d500f
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This moves the STM32 based boards (Nucleo F103RB and STM32 Mini A15) to
the "new" pinmux model.
Change-Id: I190df271a6b83fafeec0b281cd4ee7cf13d7e7db
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Add support for use of HSE (incorrectly named PREDIV1)as input of PLL,
along with HSE bypass for stabilized external clock, and XTPRE
prescaler. Update PLL handling so that we do not unnecessarily enable
PLL clocks, instead enabling only the clocks sources that are required
as per user's configuration.
This change allows higher SYSCLK clock values, up to 72MHz.
Change-Id: Ia7c2be3ce11ac0de2efa664b20e7ab5fddd57a51
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Add mapping of registers for embedded flash controller.
Change-Id: I81f891551124e9f124ff59dfe0b3c737ec5b3b63
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Add a driver for Independent Watchdog (IWDG) commonly found in STM32
MCUs. The driver has been tested on STM32F1 family MCU.
Change-Id: Idc6ac35990e46901a206b4af0ce3767eb4875de9
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Add necessary integration for supporting interrupts on GPIO input pins
for STM32F1 line of MCUs.
Change-Id: I0526a85cc3fdb96891c93ba4840ef27d613ab31b
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Add mapping of Alternate Function I/O (AFIO) registers for STM32F1 MCU.
Change-Id: Id3e12290d6869c1f0506549f21407b3cd80d0a64
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Introcuce a driver for External Interrupt/Event Controller (EXTI) found
on STM32 MCUs.
Change-Id: Ib206521fcc51b5dfaaf5dea9d436f8304f3a36be
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Add a list of symbolic constants for IRQ lines available on
STM32F1 line of MCUs.
Change-Id: Iebf1847719c0db31cf852529fe5876e3cabbfe52
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Add necessary integration code enabling use of common STM32 pinmux
driver.
The alternate function listing currently consists of USART1 pins
only. The listing should be updated when support for more devices is
added.
Change-Id: Ic65aeea9df9aaea7636ecdd6996f56e6ef59dc2f
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Add functions required for integration with common STM32 GPIO driver.
Change-Id: Ic6637e991f5c0cf659f3b927ed47ef482b13b64f
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
The patch adds a driver for STM32F10x series RCC (Reset and Clock
Control) subsystem.
The module is primarily responsible for setting up of MCU's clock
tree. In particular the driver sets up SYSCLK, PLL (with source
configuration), AHB prescaler, and APB1/APB2 prescalers. As part of this
functionality, the subsystem can enable/disable clock signal for
particular peripherals, thus reducing the power consumption of the MCU.
The driver implements clock control driver API. However, subsystem IDs
being HW specific are exposed in driver public header that must be
included by callers. The driver registers a single device using a common
name STM32_CLOCK_CONTROL_NAME. The device is initialized at
the PRIMARY level with priority 1. This allows the initialization to
take place right after SoC initialization routine.
The driver depends on selection of SOC_STM32F1X config option and is MCU
specific.
Change-Id: I8bea5db20726a24bce7b7ffe0b95de543240429a
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
The patch introduces a new family of SoCs based on STMicroelectronics'
STM32 MCU line. The patch introduces a basic arch/arm/soc layout along
with configuration of 2 MCUs from STM32F1 series: STM32F103VE and
STM32F103RB.
The patch assumes that other MCUs from STM32 family will be included
under arch/arm/soc/st_stm32 tree, to achieve the following layout:
arch/
arm/
soc/
st_stm32/
stm32f0/
stm32f1/
stm32f2/
...
stm32l0/
Most of the configuration within a single MCU family (ex. STM32F1) is
shared, however individual MCUs differ with respect to SRAM size, flash
size or the number of available peripherals. The patch assumes that per
MCU line Kconfig.soc.family file should introduce basic setup for given
series. This can be further tuned by per MCU files, with
Kconfig.soc.stm32f103rb and Kconfig.soc.stm32f103ve as examples.
Each family defines a configuration option, ex. CONFIG_STM32F10X, while
individual MCUs define a corresponding per MCU config options,
ex. CONFIG_STM32F103VE.
From the menuconfig perspective, the user is presented with a family
selection under General Platform Configuration/SoC Selection. A
specific MCU model can be selected by accessing General Platform
Configuration/STM32F1x MCU Selection, with the default entry being
selected by the board configuration.
Change-Id: I22e4defd4a08ed1b2e2cad0e214b34f565e08831
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
