pinmux/stm32: extend pinmux driver functionality to support STM32F3X series MCUs
Change-Id: Ifc4c93e03b6593f1b6c7e664fdf719f9344fe1ee Signed-off-by: Adam Podogrocki <adam.podogrocki@rndity.com>
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2 changed files with 12 additions and 7 deletions
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@ -30,7 +30,12 @@
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#include <stm32f1xx.h>
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/* IO pin functions */
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/* IO pin functions are mostly common across STM32 devices. Notable
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* exception is STM32F1 as these MCUs do not have registers for
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* configuration of pin's alternate function. The configuration is
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* done implicitly by setting specific mode and config in MODE and CNF
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* registers for particular pin.
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*/
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enum stm32f10x_pin_config_mode {
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STM32F10X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
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STM32F10X_PIN_CONFIG_BIAS_PULL_UP,
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@ -51,12 +51,7 @@ static int enable_port(uint32_t port, struct device *clk)
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}
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/* TODO: Merge this and move the port clock to the soc file */
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#if defined(CONFIG_SOC_SERIES_STM32F1X) || defined(CONFIG_SOC_SERIES_STM32L4X)
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clock_control_subsys_t subsys = stm32_get_port_clock(port);
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return clock_control_on(clk, subsys);
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#elif CONFIG_SOC_SERIES_STM32F4X
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#ifdef CONFIG_SOC_SERIES_STM32F4X
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struct stm32f4x_pclken pclken;
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/* AHB1 bus for all the GPIO ports */
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@ -64,6 +59,11 @@ static int enable_port(uint32_t port, struct device *clk)
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pclken.enr = ports_enable[port];
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return clock_control_on(clk, (clock_control_subsys_t *) &pclken);
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#else /* SOC_SERIES_STM32F1X || SOC_SERIES_STM32F3X || SOC_SERIES_STM32L4X */
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clock_control_subsys_t subsys = stm32_get_port_clock(port);
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return clock_control_on(clk, subsys);
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#endif
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}
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