To reduce the interrupt latency of MIWU events, the driver prepares a
dedicated callback function item list for each MIWU group in this PR. We
needn't check the MIWU table and group of the event in ISR. And the
maximum item number of each list is also limited to 8. After applying
this PR, the interrupt latency reduces to ~10us consistently.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Following zephyr's style guideline, all if statements, including single
line statements shall have braces.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This corrects the following:
1. The priority of type cast is lower than member access. So don't need
the redundant parentheses.
2. The macro should be added to the parentheses.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
TWDT0 is loaded with a new value and the counter restarts counting with
it by written RST bit in Timer Control register (T0CSR) to 1. Then, the
RST bit in T0CSR register is cleared automatically on the 2nd rising
edge of T0IN clock. Since TWCP is set to 1:32, the maximum time that RST
bit is unset is 32 * (1 / 32768) ~= 980us.
Polling this bit within a critical section in current npcx watchdog
driver isn't a good approach since it might block the other interrupts
need to service them in time. This CL introduces a timeout mechanism and
removes the critical section to improve this disadvantage. Consider the
clock tolerance, 2 ms is a suitable timeout value for RST bit. We also
remove polling for WD_RUN bit in T0CSR. Npcx watchdog needs serval LFCLK
(32k Hz) clocks to stop watchdog. 1 ms is long enough for the timeout
mechanism.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The source clock of the watchdog module is selected to the input of T0
timer, not output. Correct the drawing in case confusing the users.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
NPCX watchdog driver has a WDT_NPCX_DELAY_CYCLES for delay the watchdog
reset time after the watchdog timeout. For some systems, users would
like to use the watchdog timeout ISR but don't reset the chip
immediately. Let the system have the final chance to ongoing the system
before the real hardware reset time. Removing the watchdog reset
waiting loop in ISR lets users decide whether wait for watchdog reset
by themself.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Register T0CSR bit 4 is WDRST_STS which is used to check whether the
chip has watchdog reset from the last power-up or vcc1_rst. WDRST_STS
hardware is design to write one clear. For the original
read-modify-write, it will reset the WDRST_STS unexpected. Add a mask
to avoid it.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
In npcx7 series, the Timer and Watchdog module (TWD) generates the
clocks and interrupts used for timing periodic functions in the system.
It also provides watchdog reset signal generation in response to a
failure detection.
The CL also includes:
— Add npcx watchdog device tree declarations.
— Zephyr watchdog api implementation.
— Add Watchdog definitions for npcx7 series in
tests/drivers/watchdog/wdt_basic_api/src/test_wdt.c for
supporting test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
