Added NETC ENETC nodes, MDIO node, and scmi power node which will
be used to power up NETC MIX in dtsi file.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
The utility may be used during development stage to get
ambiq platform specific timing parameters for mspi devices.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
This device driver supports ISSI is25w/lx032/64 series flash.
Only extended SPI mode(1s-1s-1s, 1s-8s-8s, 1s-1s-8s) is implemented.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
Adds a common vendor dts file specifying the default partition
layout for nRF54L05-based cpuapp board targets and updates boards
to use this common file. This also drops the secure/non-secure split
in the partitioning as this was reducing NVM storage that is not
used by this board target and fixes the wrong flash field in
twister yaml files
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Adds a common vendor dts file specifying the default partition
layout for nRF54L15-based cpuapp_ns board targets and updates boards
to use this common file.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Adds a common vendor dts file specifying the default partition
layout for nRF54L15-based cpuapp board targets and updates boards
to use this common file. This also drops the secure/non-secure split
in the partitioning as this was reducing NVM storage that is not
used by this board target and fixes the wrong flash field in
twister yaml files
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Adds a common vendor dts file specifying the default partition
layout for nRF54L10-based cpuapp board targets and updates boards
to use this common file. This also drops the secure/non-secure split
in the partitioning as this was reducing NVM storage that is not
used by this board target and fixes the wrong flash field in
twister yaml files
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Add support for setting RGMII RX and TX internal delays via DT properties:
`ti,rx-internal-delay` and `ti,tx-internal-delay`.
Signed-off-by: Venkatesh Odela <venkatesh.odela@amd.com>
Add GPIO A-K nodes to the device tree for STM32MP2 SoC.
Note that GPIOs are disabled by default in the STM32MP2 SoC.
Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
Remove gpio clock management from the GPIO driver when running on the
cortex-m33 on the mp2 and gpio clocks are managed by the cortex-A, being
the resource manager, allowed by the Resource Isolation Framework (RIF).
Also add a specific binding for the mp2 gpio to make clock property
optional.
Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
Introduce DeviceTree binding for the STM32MP2 RCC clock controller,
enabling support for STM32MP2-specific clock configuration in Zephyr.
Update Kconfig.stm32 to add a dependency on STM32MP2 configuration,
allowing the use of STM32 LL RCC features when targeting STM32MP2
devices.
Add header for STM32MP2 per peripheral clock definitions.
Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
Add the mp2 exti2 dts to the dtsi file.
Add mp2 exti hal and ll function calls with EXTI2 instance. We use the
EXTI2 instance because it contains the GPIO interrupts in the non-secure
context. (We are trying to build the blinky sample as a first milestone)
Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
Add the initial device tree source include (dtsi) files for the
stm32mp25 series boards, covering non-secure configuration for zephyr on
the Cortex-M33 core.
These files provide the basic hardware description, including CPU
(Cortex-M33), memory, RCC clock controller and NVIC interrupt
controller.
Key features:
- Set flash and RAM addresses to DDR memory.
- Adjust RCC peripheral address for non-secure context.
Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
Support three different FIFO contents which are selectable through
a new DT property, fifo-mode-sel, which may be set to one of the
following values:
- 0x0 # 1x Accelerometer @12bit and 1x temperature @12bit samples
- 0x1 # 1x Accelerometer @16bit sample
- 0x2 # 2x Accelerometer @8bit samples (previous and current)
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Adapt MAX32690 driver to use Wrap_MXC_CAN_Init to handle differences
in the MSDK API (see analogdevicesinc/msdk#1306) between the
MAX32690 and MAX32662.
can_driver_api.timing_min required phase_seg1 >= 3 and phase_seg2 >= 2
when configuring CAN bit timing. Both microcontrollers covered by this
driver (MAX32662, MAX32690) support values down to 1 for both of these
timing parameters.
Refer to the docs for registers CAN_BUSTIM1, CANn_BUSTIM1.
Add a can0 node to the MAX32662 dtsi.
Signed-off-by: Ioan Dragomir <ioan.dragomir@analog.com>
Add devicetree to support for Renesas RZ/V2N
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Add SoC support and device trees for Texas Instruments AM2434 SoC. Both R5
and M4 cores are supported here.
Signed-off-by: Amneesh Singh <a-singh7@ti.com>
The driver originally supported only it8xxx2 series. This updates
introduces compatibility allow it to also support it51xxx series
with minimal changes.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit adds support for configuring the power/performance
profile for the siwx91x device using a generic
'power-profile' property in DeviceTree.
The property is available for NWP nodes,
allowing flexible selection of power management
profiles per application or board via overlay.
Signed-off-by: S Mohamed Fiaz <fiaz.mohamed@silabs.com>
Add ELC nodes to RA SoC DTS files and provide
device-specific ELC signal enums for Devicetree bindings
Signed-off-by: Khanh Nguyen <khanh.nguyen.wz@bp.renesas.com>
Add support for the Renesas RA Event Link Controller, including
driver sources, Kconfig, and Devicetree bindings.
Signed-off-by: Khanh Nguyen <khanh.nguyen.wz@bp.renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Fixes the JEDEC-ID value of the W25Q32JVWJ on-chip flash of RT1024.
It was incorrectly set to the value for the different IS25WP064 chip.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Microchip is adding more non-MEC devices to Zephyr such as
SAM and PIC32. Each device family will have its own subfolder.
We moved the existing MEC DTSI files into a new mec subfolder.
We also updated the existing MEC boards include paths.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Add information about nfct node status. For cpuapp status is irrelevant
because NFCT is by default assigned to cpuapp but for cpurad node needs
to have reserved status.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Use nordic,nrf-nfct-v2 compatible in the main nrf54h20 devicetree
description.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Configure the active discharge feature for both the BUCK and LDO/LDSW
blocks through the appropriate registers.
Signed-off-by: Jordan Yates <jordan@embeint.com>
As a software construct that depends upon Bluetooth being enabled,
this device should not be enabled by default. Most nRF SoC's have
internal `RNG` hardware that is much more efficient to access.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Explicitly enable `rng_hci` on nRF5340 application core boards, as the
application core dos not have access to a dedicated RNG hardware
peripheral (limited to the network core).
Signed-off-by: Jordan Yates <jordan@embeint.com>
