1. Update the way test_i2s_state_error_neg test handles
RX overflow.
2. Clean up after test_i2s_state_stopping_neg test in case the
receiving channel is stuck in the STOPPING State if the data
was received prior to calling the STOP trigger.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
1. Allow loopback over different I2S ports
2. Add a config option to indicate if the ports
are separate
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
1. Provide an option to loopback over separate I2S ports
2. Increase the buffer count in the loopback test to 4
3. Update test_i2s_transfer_rx_overrun test on how to
handle RX overrun failures
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
1. Update the SDK API's called in the configure implementation.
The DMA_PrepareTransfer and DMA_SubmitTransfer SDK functions
are not recommneded for use. Replaced the call to these SDK
functions with other SDK API's.
2. Fix the implementation the configure function when multiple
blocks are used.
3. Update the dma_reload implementation. The old reload function
would simply abort the transfer. The new implementation reloads
the DMA buffers for transfer.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Move the STM32F0 specific ram vector table sections into a dedicated
linker snippet included by the new `SRAM_VECTOR_TABLE` symbol.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Add a new Kconfig symbol that explicitly controls whether the vector
table should be placed in RAM. This eliminates the side effect of
`IS_BOOTLOADER` controlling vector table location. Making the condition
a positive assertion also allows the config to be used in CMakeLists
conditions (`zephyr_linker_sources_ifdef()`, etc).
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Remove the `IS_BOOTLOADER` and `BOOTLOADER_SRAM_SIZE` symbols from the
`nucleo_l053r8` and `nucleo_l031k6` boards. The stated reason for
inclusion is to disable the RAM vector table, however this doesn't apply
to the STM32L0 series, only STM32F0.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Initialize `handle.device` to `None` so that the assert after the
matching has a chance to catch errors. Without this, a failed match will
raise an exception on the line above as it attempts to get a property
that doesn't exist.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Document the fact than NVS image of different wbs
are compatible each other if psychical ATE size
is kept.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Signed-off-by: Damian Krolik <damian.krolik@nordicsemi.no>
When existing records stored in the NVS are not properly
aligned according to the current flash driver requirements,
fs->data_wra may be initialized with an unaligned address.
Fix the initialization code, so that fs->data_wra is rounded
up to the nearest multiple of the current flash driver block
size.
The situation may occur during a firmware upgrade which
introduces a new flash driver or changes its parameters.
Signed-off-by: Damian Krolik <damian.krolik@nordicsemi.no>
Remove undefined functions (unsued anymore).
Add missing stub implementation for new DF related radio functions.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
Add Radio configuration API that gives possiblity configure
reception and sampling of CTE.
Part of alrady implemented API was re-factored to comply
with new API and do complete initialization of registers:
DFECTRL1 and CTEINLINECONF.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
The network tests were expecting that network interfaces
are in certain order. As we cannot guarantee that, refactor
the tests like this:
* if test is using DUMMY L2 driver, then disable Ethernet L2
and fetch only DUMMY L2 instead of default interface
* if test is using Ethernet L2 driver, then make sure that the
test is using the Ethernet interface specified in the test
instead of the one provided by the DUT
Fixes#34505
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
This adds the bits to the gen_mmu.py script so that extra mappings
can be added with caching disabled. This is useful for mapping
MMIO regions where caching is not desired.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit enables flash support for stm32h747i_disco_m7
in device tree. This has been tested with flash sample
application on stm32h747i_disco platform with m7 core.
Flash is shared between two cores (M4 & M7) so the last 1M is
assigned to M4 core. Hence allocating 1M of storage at the
end of first 1M.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
There is a possibility that the DWT frequency calculation
is divided by zero. So this fixes the issue by repeatedly
trying to get the delta clock cycles and delta DWT cycles
until they both are not zero.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There is a possibility that the TSC frequency calculation
is divided by zero. So this fixes the issue by repeatedly
trying to get the delta clock cycles and delta TSC cycles
until they both are not zero.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The use of device_pm_control_nop is deprecated so remove it
from the test as it will give warning in CI.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Add binding fro stm32wl-rcc.yaml that derivates from stm32wb-rcc.
Additionally update stm32wb-pll-clock.yaml to be used as well
for stm32wl series and add missing div-m property.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add support for STM32L0 clocks bindings.
Also, add a small tweak to SYSCLK selection to factorize some lines.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add clocks node and clocks to stm32l5 series.
PLL binding is reused from stm32l4 series.
Matching binding is updated to document that.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add clocks nodes for F0/F3/G0/G4 series.
For F0 and G0 series, update compatible for rcc node
to specify use of dedicated "st,stm32f0-rcc" compatible.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add bindings for F0/F3/G0/G4 clocks.
Introduce new rcc binding "st,stm32f0-rcc" binding
that describes RCC hardware blocks that don't have
"apb2-prescaler".
This binding also applies to G0.
Binding "st,stm32f0-pll-clock" is used for both F0
and F3 series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
