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boards: nucleo_l552ze_q: Use dts for clocks configuration

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Convert board to use of device tree for clocks configuration.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2021-04-14 16:51:14 +02:00 • committed by Carles Cufí
commit 367c06252d
3 changed files with 25 additions and 39 deletions
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23
boards/arm/nucleo_l552ze_q/nucleo_l552ze_q-common.dtsi
View file

@ -34,6 +34,29 @@
};
};
&clk_msi{
status = "okay";
msi-range = <6>;
};
&pll {
div-m = <1>;
mul-n = <55>;
div-p = <7>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_msi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(110)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
};
&rng {
status = "okay";
};

21
boards/arm/nucleo_l552ze_q/nucleo_l552ze_q_defconfig
View file

@ -2,8 +2,6 @@
CONFIG_SOC_SERIES_STM32L5X=y
CONFIG_SOC_STM32L552XX=y
# 110MHz system clock
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=110000000
# enable uart driver
CONFIG_SERIAL=y
@ -14,25 +12,8 @@ CONFIG_PINMUX=y
# enable GPIO
CONFIG_GPIO=y
# clock configuration
# Enable clock
CONFIG_CLOCK_CONTROL=y
# SYSCLK selection
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# PLL configuration
CONFIG_CLOCK_STM32_PLL_SRC_MSI=y
CONFIG_CLOCK_STM32_MSI_RANGE=6
#CONFIG_CLOCK_STM32_LSE=y
#CONFIG_CLOCK_STM32_MSI_PLL_MODE=y
# produce 110MHz clock at PLL output
CONFIG_CLOCK_STM32_PLL_M_DIVISOR=1
CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=55
CONFIG_CLOCK_STM32_PLL_P_DIVISOR=7
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=2
CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2
CONFIG_CLOCK_STM32_AHB_PRESCALER=1
CONFIG_CLOCK_STM32_APB1_PRESCALER=1
CONFIG_CLOCK_STM32_APB2_PRESCALER=1
# console
CONFIG_CONSOLE=y

20
boards/arm/nucleo_l552ze_q/nucleo_l552ze_q_ns_defconfig
View file

@ -2,8 +2,6 @@
CONFIG_SOC_SERIES_STM32L5X=y
CONFIG_SOC_STM32L552XX=y
# 110MHz system clock
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=110000000
# enable uart driver
CONFIG_SERIAL=y
@ -14,24 +12,8 @@ CONFIG_PINMUX=y
# enable GPIO
CONFIG_GPIO=y
# clock configuration
# Enable clock
CONFIG_CLOCK_CONTROL=y
# SYSCLK selection
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# PLL configuration
CONFIG_CLOCK_STM32_PLL_SRC_MSI=y
CONFIG_CLOCK_STM32_MSI_RANGE=6
#CONFIG_CLOCK_STM32_LSE=y
#CONFIG_CLOCK_STM32_MSI_PLL_MODE=y
# produce 110MHz clock at PLL output
CONFIG_CLOCK_STM32_PLL_M_DIVISOR=1
CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=55
CONFIG_CLOCK_STM32_PLL_P_DIVISOR=7
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=2
CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2
CONFIG_CLOCK_STM32_AHB_PRESCALER=1
CONFIG_CLOCK_STM32_APB1_PRESCALER=1
CONFIG_CLOCK_STM32_APB2_PRESCALER=1
# console
CONFIG_CONSOLE=y