As already done for the regular linker script, dinamically generates the
memory regions with the 'zephyr,memory-region' compatible also when
using the cmake linker generator.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Introduce a new "zephyr,memory-region" compatible to be used when a new
memory region must be created in the linker script from the devicetree
nodes using the compatible.
Remove also the LINKER_DT_REGION_FROM_NODE macro and add a new
LINKER_DT_REGIONS macro to cycle through all the compatible regions.
In the same PR modify the DTS files and the linker scripts.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add a new cmake extension function:
dt_comp_path(<var> COMPATIBLE <compatible> [INDEX <idx>])
to get a list of paths for the nodes with the given <compatible>. This
is useful when we have to cycle through several nodes with the same
compatible.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This enables the below configuration so the AP and EC are able to
communicate over eSPI:
CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION
CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
This align the RISC-V linker script with ARM linker script.
(The snippets-ram-sections.ld is included first inside the
RAMABLE_REGION)
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
When sleep modes are used, configure sockets
to restore on boot. Letting the HL7800 manage
this means the driver does not have to do it.
Signed-off-by: Ryan Erickson <ryan.erickson@lairdconnect.com>
- Prevent double callback with ADV re-scheduling
For configurations using CONFIG_BT_CTLR_JIT_SCHEDULING, when last
ADV before initiating connection is re-scheduled with a small delay,
the disabled_cb would be called a second time. This would unexpectedly
invoke a second conn setup with illegal parameters.
To avoid this JIT scheduler phenomenon, clear the ADV disabled_cb
when invoked.
- Add priority to LLL header. This allows the conn priority to be
associated with the object. Used in vendor LLL implementation.
Signed-off-by: Morten Priess <mtpr@oticon.com>
Currently, the DCACHE range invalidation can cause data corruption when
the ends of the given range is not aligned to a full cache line.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Do not retransmit a message that just has been send successfully.
This case can in particular happen quite frequently if the modem
connection/throughput is quite bad and so there is a high latency.
A message that has to be acknowledged is scheduled for retransmission.
Before retransmission a ack for this message is received that will
cause a reset of the original message. In this case you see a
"LwM2M message is invalid" error message.
Signed-off-by: Andreas Chmielewski <andreas.chmielewski@grandcentrix.net>
fixtures could also be given by twister command with --fixture option
explicitly, not only hardware map file. In this case, we should
assign those fixtures to each devices too.
Signed-off-by: Chen Peng1 <peng1.chen@intel.com>
No reason to exclude this platform, we only have been using wrong
logging defaults (which was set in the soc) and not printing log
messages which is required by the test.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
We are enabling logging in the SoC, this should be an application
decision, not a hardware decision.
Additionally, we are disabling logging defaults for testing, which
results in some tests failing on those platforms due to missing messages
in the test output.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
After PR: https://github.com/zephyrproject-rtos/zephyr/pull/38296
If we receive the second recovery after 192 hours after the first
recovery, we may still not be able to perform any recovery, even
if the IV Index differs by 42, because the `ivi_was_recovered` flag
will only be cleared during the iv update.
But still May lose iv update, as we did the first iv recovery.
This patch by checking the iv duration, if 192h later, auto clear
`ivi_was_recovered` flag.
Signed-off-by: Lingao Meng <menglingao@xiaomi.com>
We don't set core numbers for mdb-hw runner for nSIM
board, so it defaults to 1, so mdb-hw runner doesn't work with
SMP boards.
Fix that.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
This adds a filter to only enable the CMOS test on PC compatible
x86 boards, as CMOS RTC is usually not present on embedded
applications.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds a filter to only tests platforms that has
CONFIG_X86_PC_COMPATIBLE enabled. ACPI, multiboot and
CMOS RTC are usually all present on PC compatible and
not embedded ones. So limit the scope here.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The last 2k bytes of the data RAM is used by the booter in some npcx EC
chips. This commit adds a bootloader_ram DT node to describe this
additional layout of the RAM. As a result, we can determine the total
RAM size by adding the size of flash0, sram0, and bootloader_ram.
Also, this commit moves 64k bytes from the code RAM (flash0) to the data
RAM (sram0) for npcx7m7fc because its internal flash is 512K bytes.
(In the Chromebook application, we need the code RAM size <= half of the
flash size.)
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Do not include psl-in related code is the status of vsby-psl-in-list is
disabled, which can help reduce a little RAM/flash size.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
The application may not always use the PSL mode. Change the status of
node vsby-psl-in-list default disabled. The application can override it
when it wants to use PSL hibernate.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This commit sets the power down bit of the module SDP, UART3, UART4,
and I3C by default. The module's driver should take the responsibility
to clear it to turn on the power. It helps reduce the power consumption
when an application doesn't use these modules.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
ARM does not guarantee the timing effects of NOP
instruction. Hence skip the test_nop test.
Fix for Issue#42666
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Reduce SPI size to maximum FLASH ram size supported
This also speed up flashing process.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
If CONFIG_ETH_NATIVE_POSIX_RANDOM_MAC=n and
CONFIG_ETH_NATIVE_POSIX_MAC_ADDR="", the MAC address can be set with a
net_mgmt call before the driver is initialized.
Signed-off-by: Björn Stenberg <bjorn@haxx.se>
Avoid executing ISRs using the thread stack as it might not be sized
for that. Plus, we do have IRQ stacks already set up for us.
The non-nested IRQ context is still (and has to be) saved on the thread
stack as the thread could be preempted.
The irq_offload case is never nested and always invoked with the
sched_lock held so it can be simplified a bit.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This is an uint32_t so the proper register width must be used, otherwise
the adjacent structure member will be overwritten (didn't happen in
practice because of struct member alignment but still). This makes the
inc_nest_counter and dec_nest_counter macros rather unwieldy, especially
with upcoming changes, so let's just remove them.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Add config to disable all TF-M output. This configuration is needed
in order to exclude the UART driver through a select in Kconfig
when either the code size optimization or the UART instance requires it.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
The ADC sampling of it8xxx2 needs to read each channel in sequence,
so it needs to wait for an interrupt to read data in the loop
through k_sem_take().
In test_adc.c, k_timer_start() is used in the interval test, so we
need to use polling wait instead of k_sem_take() to wait, otherwise
it will cause kernel panic.
k_is_in_isr() can determine whether to use polling or k_sem_take()
at present.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Read operation must return empty payload when read /object_id
if there is no created object instances.
Signed-off-by: Juha Heiskanen <juha.heiskanen@nordicsemi.no>
Let's provide our own z_early_memset() and z_early_memcpy() rather than
making our own .bss clearing function that risk missing out on updates
to the main version.
Also remove extra stuff already provided by kernel_internal.h.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Zeroing the BSS and copying data to RAM with regular memset/memcpy may
cause problems when those functions are assuming a fully initialized
system for their optimizations to work e.g. some instructions require
an active MMU, but turning the MMU on needs the .bss section to be
cleared first, etc.
Commit c5b898743a ("aarch64: Fix alignment fault on z_bss_zero()")
provides a detailed explanation of such a case.
Replacing z_bss_zero() with an architecture specific one is problematic
as the former may see new sections added to it that would be missed by
the later. The same reasoning goes for z_data_copy().
Let's make maintenance much easier by providing weak versions of
memset/memcpy that can be overridden by architecture-specific safe
versions when needed.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Failures to boot are not exclusive to the cavstool.py, they can happen
with the kernel driver and --log-only too. For such a situation this
commit adds a useful delay and these two log lines (before the mmap
crashes eventually):
INFO:cavs-fw:Waiting for firmware handoff, FW_STATUS = 0x81000012
WARNING:cavs-fw:Load failed? FW_STATUS = 0x1006701
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Clarify that the reader MUST track the last sequence number read and
that the 'start' offset is not involved in that.
Some pre-conceptions + the sentence "the current state of the stream"
threw me off for a while. Thanks Andy for explaining this to me.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Makes the IRQ_CONNECT macro statically declarable for Xtensa (nothing
prevented it except its structuring). Allows for IRQ_CONNECT usage
on a xtensa only platform to be declared statically avoiding the
fluff of setting up and enabling irqs for cavs gpdma.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Intel's adsp needs to set, at a minimum, a clocking bit before the driver
can initialize the designware dma controller. In many ways it is the
designware dmac IP but with additional registers and functionality added
on top of it. So the code structure here follows how the hardware
appears to be designed, layered on top of the designware driver.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Move most of the designware driver into a common compile unit with a
a header that exposes the common functionality.
This allows for derivative hardware, such as that in intel's adsp (cavs)
to use the common functionality while extending.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
