ITE: drivers/adc: fix the sampling flow of ADC
The ADC sampling of it8xxx2 needs to read each channel in sequence, so it needs to wait for an interrupt to read data in the loop through k_sem_take(). In test_adc.c, k_timer_start() is used in the interval test, so we need to use polling wait instead of k_sem_take() to wait, otherwise it will cause kernel panic. k_is_in_isr() can determine whether to use polling or k_sem_take() at present. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit is contained in:
Tim Lin
Anas Nashif
parent
60088b18d4
commit
4381841bd8
1 changed files with 135 additions and 58 deletions
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@ -24,6 +24,10 @@ LOG_MODULE_REGISTER(adc_ite_it8xxx2);
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#define IT8XXX2_ADC_VREF_VOL 3000
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/* ADC channels disabled */
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#define IT8XXX2_ADC_CHANNEL_DISABLED 0x1F
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/* ADC sample time delay (Unit:us) */
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#define IT8XXX2_ADC_SAMPLE_TIME_US 200
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/* Wait next clock rising (Clock source 32.768K) */
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#define IT8XXX2_WAIT_NEXT_CLOCK_TIME_US 31
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/* List of ADC channels. */
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enum chip_adc_channel {
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@ -40,6 +44,7 @@ enum chip_adc_channel {
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struct adc_it8xxx2_data {
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struct adc_context ctx;
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struct k_sem sem;
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/* Channel ID */
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uint32_t ch;
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/* Save ADC result to the buffer. */
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@ -100,20 +105,6 @@ static int adc_it8xxx2_channel_setup(const struct device *dev,
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return 0;
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}
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static void adc_enable_measurement(uint32_t ch)
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{
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struct adc_it8xxx2_regs *const adc_regs = ADC_IT8XXX2_REG_BASE;
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/* Select and enable a voltage channel input for measurement */
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adc_regs->VCH0CTL = (IT8XXX2_ADC_DATVAL | IT8XXX2_ADC_INTDVEN) + ch;
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/* Enable adc interrupt */
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irq_enable(DT_INST_IRQN(0));
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/* ADC module enable */
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adc_regs->ADCCFG |= IT8XXX2_ADC_ADCEN;
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}
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static void adc_disable_measurement(void)
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{
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struct adc_it8xxx2_regs *const adc_regs = ADC_IT8XXX2_REG_BASE;
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@ -131,6 +122,89 @@ static void adc_disable_measurement(void)
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irq_disable(DT_INST_IRQN(0));
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}
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/* Get result for each ADC selected channel. */
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static void adc_it8xxx2_get_sample(const struct device *dev)
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{
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struct adc_it8xxx2_data *data = dev->data;
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struct adc_it8xxx2_regs *const adc_regs = ADC_IT8XXX2_REG_BASE;
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if (adc_regs->VCH0CTL & IT8XXX2_ADC_DATVAL) {
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/* Read adc raw data of msb and lsb */
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*data->buffer++ = adc_regs->VCH0DATM << 8 | adc_regs->VCH0DATL;
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} else {
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LOG_WRN("ADC failed to read (regs=%x, ch=%d)",
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adc_regs->ADCDVSTS, data->ch);
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}
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adc_disable_measurement();
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}
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static void adc_poll_valid_data(void)
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{
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struct adc_it8xxx2_regs *const adc_regs = ADC_IT8XXX2_REG_BASE;
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const struct device *dev = DEVICE_DT_INST_GET(0);
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int valid = 0;
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/*
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* If the polling waits for a valid data longer than
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* the sampling time limit, the program will return.
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*/
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for (int i = 0U; i < (IT8XXX2_ADC_SAMPLE_TIME_US /
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IT8XXX2_WAIT_NEXT_CLOCK_TIME_US); i++) {
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/* Wait next clock time (1/32.768K~=30.5us) */
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k_busy_wait(IT8XXX2_WAIT_NEXT_CLOCK_TIME_US);
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if (adc_regs->VCH0CTL & IT8XXX2_ADC_DATVAL) {
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valid = 1;
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break;
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}
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}
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if (valid) {
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adc_it8xxx2_get_sample(dev);
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} else {
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LOG_ERR("Sampling timeout.");
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return;
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}
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}
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static void adc_enable_measurement(uint32_t ch)
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{
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struct adc_it8xxx2_regs *const adc_regs = ADC_IT8XXX2_REG_BASE;
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const struct device *dev = DEVICE_DT_INST_GET(0);
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struct adc_it8xxx2_data *data = dev->data;
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/* Select and enable a voltage channel input for measurement */
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adc_regs->VCH0CTL = (IT8XXX2_ADC_DATVAL | IT8XXX2_ADC_INTDVEN) + ch;
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/* ADC module enable */
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adc_regs->ADCCFG |= IT8XXX2_ADC_ADCEN;
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/*
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* In the sampling process, it is possible to read multiple channels
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* at a time. The ADC sampling of it8xxx2 needs to read each channel
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* in sequence, so it needs to wait for an interrupt to read data in
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* the loop through k_sem_take(). But k_timer_start() is used in the
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* interval test in test_adc.c, so we need to use polling wait instead
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* of k_sem_take() to wait, otherwise it will cause kernel panic.
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*
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* k_is_in_isr() can determine whether to use polling or k_sem_take()
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* at present.
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*/
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if (k_is_in_isr()) {
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/* polling wait for a valid data */
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adc_poll_valid_data();
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} else {
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/* Enable adc interrupt */
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irq_enable(DT_INST_IRQN(0));
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/* Wait for an interrupt to read data valid. */
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if (k_sem_take(&data->sem, K_MSEC(1))) {
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LOG_ERR("ADC interrupt is not fired.");
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return;
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}
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}
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}
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static int check_buffer_size(const struct adc_sequence *sequence,
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uint8_t active_channels)
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{
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@ -167,6 +241,8 @@ static int adc_it8xxx2_start_read(const struct device *dev,
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}
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LOG_DBG("Configure resolution=%d", sequence->resolution);
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data->buffer = sequence->buffer;
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adc_context_start_read(&data->ctx, sequence);
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return adc_context_wait_for_completion(&data->ctx);
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@ -176,41 +252,60 @@ static void adc_context_start_sampling(struct adc_context *ctx)
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{
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struct adc_it8xxx2_data *data =
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CONTAINER_OF(ctx, struct adc_it8xxx2_data, ctx);
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uint32_t channels = ctx->sequence.channels;
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uint8_t channel_count = 0;
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data->repeat_buffer = data->buffer;
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adc_enable_measurement(data->ch);
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/*
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* The ADC sampling of it8xxx2 needs to read each channel
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* in sequence.
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*/
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while (channels) {
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data->ch = find_lsb_set(channels) - 1;
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channels &= ~BIT(data->ch);
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adc_enable_measurement(data->ch);
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channel_count++;
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}
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if (check_buffer_size(&ctx->sequence, channel_count)) {
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return;
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}
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adc_context_on_sampling_done(&data->ctx, DEVICE_DT_INST_GET(0));
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}
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static int adc_it8xxx2_read(const struct device *dev,
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const struct adc_sequence *sequence)
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{
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struct adc_it8xxx2_data *data = dev->data;
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uint32_t channel_mask = sequence->channels;
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uint8_t channel_count = 0;
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int err = 0;
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int err;
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data->buffer = sequence->buffer;
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while (channel_mask) {
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adc_context_lock(&data->ctx, false, NULL);
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data->ch = find_lsb_set(channel_mask) - 1;
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err = adc_it8xxx2_start_read(dev, sequence);
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if (err) {
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return err;
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}
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channel_mask &= ~BIT(data->ch);
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channel_count++;
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adc_context_release(&data->ctx, err);
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}
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err = check_buffer_size(sequence, channel_count);
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adc_context_lock(&data->ctx, false, NULL);
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err = adc_it8xxx2_start_read(dev, sequence);
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adc_context_release(&data->ctx, err);
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return err;
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}
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#ifdef CONFIG_ADC_ASYNC
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static int adc_it8xxx2_read_async(const struct device *dev,
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const struct adc_sequence *sequence,
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struct k_poll_signal *async)
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{
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struct adc_it8xxx2_data *data = dev->data;
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int err;
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adc_context_lock(&data->ctx, true, async);
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err = adc_it8xxx2_start_read(dev, sequence);
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adc_context_release(&data->ctx, err);
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return err;
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}
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#endif /* CONFIG_ADC_ASYNC */
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static void adc_context_update_buffer_pointer(struct adc_context *ctx,
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bool repeat_sampling)
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{
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@ -222,28 +317,6 @@ static void adc_context_update_buffer_pointer(struct adc_context *ctx,
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}
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}
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/* Get result for each ADC selected channel. */
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static void adc_it8xxx2_get_sample(const struct device *dev)
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{
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struct adc_it8xxx2_data *data = dev->data;
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struct adc_it8xxx2_regs *const adc_regs = ADC_IT8XXX2_REG_BASE;
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bool valid = false;
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if (adc_regs->VCH0CTL & IT8XXX2_ADC_DATVAL) {
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/* Read adc raw data of msb and lsb */
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*data->buffer++ = adc_regs->VCH0DATM << 8 | adc_regs->VCH0DATL;
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valid = 1;
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}
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if (!valid) {
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LOG_WRN("ADC failed to read (regs=%x, ch=%d)",
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adc_regs->ADCDVSTS, data->ch);
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}
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adc_disable_measurement();
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}
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static void adc_it8xxx2_isr(const void *arg)
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{
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struct device *dev = (struct device *)arg;
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@ -253,12 +326,15 @@ static void adc_it8xxx2_isr(const void *arg)
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adc_it8xxx2_get_sample(dev);
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adc_context_on_sampling_done(&data->ctx, dev);
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k_sem_give(&data->sem);
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}
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static const struct adc_driver_api api_it8xxx2_driver_api = {
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.channel_setup = adc_it8xxx2_channel_setup,
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.read = adc_it8xxx2_read,
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#ifdef CONFIG_ADC_ASYNC
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.read_async = adc_it8xxx2_read_async,
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#endif
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.ref_internal = IT8XXX2_ADC_VREF_VOL,
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};
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@ -313,6 +389,7 @@ static int adc_it8xxx2_init(const struct device *dev)
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IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
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adc_it8xxx2_isr, DEVICE_DT_INST_GET(0), 0);
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k_sem_init(&data->sem, 0, 1);
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adc_context_unlock_unconditionally(&data->ctx);
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return 0;
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