Chip siwx91x has 672kB of SRAM shared between the Cortex-M4 (Zephyr) and
the NWP (Network Processor). 3 memory configurations are possible for
the Cortex-M4:
- 196kB
- 256kB
- 320kB
Less memory is allocated to Zephyr, more memory is allocated to NWP,
better are the WiFi and BLE performances.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Some instances of DMA (dma0) can use the normal sram to store their
descriptors. In this case, it makes sense to allow the linker to
allocate the memory rather than tweaking the memory layout.
So, if the attribute silabs,sram-region is not defined, use a statically
allocated buffer.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Memory areas for DMA descriptors are shared with the DMA hardware block.
There area should be cached by the CPU.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Silabs siwx91x hardware use specific memory areas to store descriptors
for DMA requests. These areas are tightly coupled between the CPU and
the hardware. This helps in reducing the wait cycles.
Until now these addresses was also hard coded in the DT and in the
linker script. This patch leverage the zephyr,memory-region driver to
centralize the information in the DT.
Then, with this new implementation, the memory mapping is easier to
understand for the reader.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Currently, siwx917 have three instances of uart: ulpuart, uart1 and
uart2. However:
- The other drivers on siwx91x (i2c, dma, i2s, etc...) rather use
'ulp', '0' and '1'.
- The reference manual also uses 'ulp', '0' and '1'.
The source of the confusion probably come from the clock driver in
WiseConnect which use clocks USART1 and USART2. However, this probably
not expected.
So, this patch renames uart1 and uart2 in uart0 and uart1. This change
also impacts the names of pins and the names of the clocks.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
A specific section of the flash on the SiWx917 is reserved for the
Network co-processor (NWP). This zone needs to be delimited in order to
not overwrite it. We then need to use "code-partition" to provide Zephyr
the application code flash location.
Co-authored-by: Martin Hoff <martin.hoff@silabs.com>
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Report DMA configuration in the board definitions.
Note the addresses of the DMA buffers are hardcoded in the HAL. So,
these areas have to be declared in the linker file.
Co-authored-by: Sai Santhosh Malae <santhosh.malae@silabs.com>
Signed-off-by: Sai Santhosh Malae <santhosh.malae@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Introduce minimal support for Silicon Labs SiWx91x family. SiWx91x
provide many device and especially Bluetooth and Wifi connectivity. This
patch prepare Zephyr to receive further drivers.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
