2bbafa7072
Chip siwx91x has 672kB of SRAM shared between the Cortex-M4 (Zephyr) and the NWP (Network Processor). 3 memory configurations are possible for the Cortex-M4: - 196kB - 256kB - 320kB Less memory is allocated to Zephyr, more memory is allocated to NWP, better are the WiFi and BLE performances. Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
322 lines
7.1 KiB
Text
322 lines
7.1 KiB
Text
/*
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* Copyright (c) 2024-2025 Silicon Laboratories Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/clock/silabs/siwx91x-clock.h>
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#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
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#include <freq.h>
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/ {
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chosen {
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zephyr,sram = &sram0;
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zephyr,entropy = &rng0;
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zephyr,flash = &flash0;
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zephyr,flash-controller = &flashctrl0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-m4f";
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reg = <0>;
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};
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};
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sram0: memory@0 {
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compatible = "mmio-sram";
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/* siwx91x has 672kB of SRAM shared between the Cortex-M4
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* (Zephyr) and the NWP (Network Processor). 3 memory
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* configurations are
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* possible:
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* - 196kB
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* - 256kB
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* - 320kB
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* Less memory is allocated to Zephyr, more memory is allocated
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* to NWP, better are the WiFi and BLE performances.
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*/
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reg = <0x00000000 DT_SIZE_K(196)>;
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};
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sram_dma1: memory-dma@24061c00 {
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x24061c00 DT_SIZE_K(1)>;
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zephyr,memory-region = "dma1";
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zephyr,memory-attr = <DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE)>;
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};
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bt_hci0: bt_hci {
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compatible = "silabs,siwx91x-bt-hci";
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status = "disabled";
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};
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wifi0: wifi {
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compatible = "silabs,siwx91x-wifi";
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status = "disabled";
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};
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soc {
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clock0: clock@46000000 {
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compatible = "silabs,siwx91x-clock";
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reg = <0x46000000 0x100>,
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<0x46000800 0x100>,
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<0x24041400 0x100>,
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<0x24048000 0x200>;
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#clock-cells = <1>;
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status = "okay";
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};
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pinctrl0: pinctrl@46130000 {
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compatible = "silabs,siwx91x-pinctrl";
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reg = <0x46130000 0x1000>;
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};
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flashctrl0: flash-controller@12000000 {
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compatible = "silabs,siwx91x-flash-controller";
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reg = <0x12000000 0x200>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@8202000 {
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compatible = "soc-nv-flash";
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write-block-size = <1>;
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erase-block-size = <4096>;
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};
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};
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ulpuart: uart@24041800 {
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compatible = "ns16550";
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reg = <0x24041800 0x1000>;
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interrupts = <12 0>;
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reg-shift = <2>;
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clocks = <&clock0 SIWX91X_CLK_ULP_UART>;
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current-speed = <115200>;
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status = "disabled";
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};
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uart0: uart@44000000 {
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compatible = "ns16550";
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reg = <0x44000000 0x1000>;
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interrupts = <38 0>;
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reg-shift = <2>;
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clocks = <&clock0 SIWX91X_CLK_UART0>;
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current-speed = <115200>;
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status = "disabled";
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};
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uart1: uart@45020000 {
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compatible = "ns16550";
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reg = <0x45020000 0x1000>;
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interrupts = <39 0>;
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reg-shift = <2>;
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clocks = <&clock0 SIWX91X_CLK_UART1>;
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current-speed = <115200>;
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status = "disabled";
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};
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rng0: rng@45090000 {
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compatible = "silabs,siwx91x-rng";
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reg = <0x45090000 0x8>;
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};
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egpio0: egpio@46130000 {
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compatible = "silabs,siwx91x-gpio";
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reg = <0x46130000 0x1260>;
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interrupts = <52 0>, <53 0>, <54 0>, <55 0>,
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<56 0>, <57 0>, <58 0>, <59 0>;
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interrupt-names = "PIN0", "PIN1", "PIN2", "PIN3",
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"PIN4", "PIN5", "PIN6", "PIN7";
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#address-cells = <1>;
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#size-cells = <0>;
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gpioa: gpio@0 {
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compatible = "silabs,siwx91x-gpio-port";
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reg = <0>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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gpio-reserved-ranges = <0 6>;
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silabs,pads = [
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ff ff ff ff ff ff 01 02 03 04 05 06 07 ff ff 08
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];
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status = "okay";
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};
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gpiob: gpio@1 {
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compatible = "silabs,siwx91x-gpio-port";
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reg = <1>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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silabs,pads = [
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ff ff ff ff ff ff ff ff ff 00 00 00 00 00 00 09
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];
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status = "okay";
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};
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gpioc: gpio@2 {
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compatible = "silabs,siwx91x-gpio-port";
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reg = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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silabs,pads = [
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09 09 09 ff ff ff ff ff ff ff ff ff ff ff 0a 0b
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];
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status = "okay";
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};
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gpiod: gpio@3 {
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compatible = "silabs,siwx91x-gpio-port";
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reg = <3>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <10>;
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silabs,pads = [
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0c 0d 0e 0f 10 11 12 13 14 15 ff ff ff ff ff ff
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];
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status = "okay";
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};
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};
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egpio1: egpio@2404c000 {
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compatible = "silabs,siwx91x-gpio";
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reg = <0x2404C000 0x1260>;
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interrupts = <18 0>;
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interrupt-names = "ULP";
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silabs,ulp;
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#address-cells = <1>;
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#size-cells = <0>;
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ulpgpio: ulpgpio@0 {
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compatible = "silabs,siwx91x-gpio-port";
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reg = <0>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <12>;
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gpio-reserved-ranges = <3 1>;
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silabs,pads = [
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16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 ff ff ff ff
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];
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status = "okay";
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};
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};
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uulpgpio: uulpgpio@24048600 {
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compatible = "silabs,siwx91x-gpio-uulp";
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reg = <0x24048600 0x30>, <0x12080000 0x18>;
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reg-names = "ret", "int";
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interrupts = <21 0>;
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interrupt-names = "UULP";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <5>;
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status = "okay";
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};
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ulpi2c: i2c@24040000 {
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compatible = "snps,designware-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x24040000 0x100>;
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interrupts = <13 0>;
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interrupt-names = "i2c2";
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clocks = <&clock0 SIWX91X_CLK_ULP_I2C>;
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status = "disabled";
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};
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i2c0: i2c@44010000 {
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compatible = "snps,designware-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x44010000 0x100>;
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interrupts = <42 0>;
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interrupt-names = "i2c0";
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clocks = <&clock0 SIWX91X_CLK_I2C0>;
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status = "disabled";
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};
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i2c1: i2c@47040000 {
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compatible = "snps,designware-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x47040000 0x100>;
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interrupts = <61 0>;
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interrupt-names = "i2c1";
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clocks = <&clock0 SIWX91X_CLK_I2C1>;
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status = "disabled";
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};
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dma0: dma@44030000 {
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compatible = "silabs,siwx91x-dma";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x44030000 0x82C>;
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interrupts = <33 0>;
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interrupt-names = "dma0";
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clocks = <&clock0 SIWX91X_CLK_DMA0>;
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#dma-cells = < 1>;
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dma-channels = <32>;
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status = "disabled";
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};
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ulpdma: dma@24078000 {
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compatible = "silabs,siwx91x-dma";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x24078000 0x82C>;
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interrupts = <10 0>;
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interrupt-names = "ulpdma";
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clocks = <&clock0 SIWX91X_CLK_ULP_DMA>;
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silabs,sram-region = <&sram_dma1>;
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#dma-cells = < 1>;
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dma-channels = <12>;
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status = "disabled";
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};
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pwm: pwm@47070000 {
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compatible = "silabs,siwx91x-pwm";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x47070000 0x14C>;
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interrupts = <48 0>;
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interrupt-names = "pwm";
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clocks = <&clock0 SIWX91X_CLK_PWM>;
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#pwm-cells = <2>;
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silabs,ch_prescaler = <64 64 64 64>;
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status = "disabled";
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};
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watchdog: wdt@24048300 {
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compatible = "silabs,siwx91x-wdt";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x24048300 0x1C>;
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interrupts = <20 0>;
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interrupt-names = "watchdog";
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clocks = <&clock0 SIWX91X_CLK_WATCHDOG>;
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status = "disabled";
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};
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sysrtc0: sysrtc@24048c00 {
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compatible = "silabs,gecko-stimer";
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reg = <0x24048c00 0x78>;
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interrupts = <22 0>;
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interrupt-names = "sysrtc";
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clock-frequency = <DT_FREQ_K(32)>;
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prescaler = <1>;
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status = "disabled";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <6>;
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};
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