Add a memory barrier to make sure write to NVIC is completed
before continuing with the test fails in scenarios where
CONFIG_ROMSTART_RELOCATION_ROM is enabled for boards like MPS3
Corstone310 and k_sem_take is called before the isr's are called.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
Enable tests by default for CS300 and CS310 since they support
simulation and FVP's are available in upstream docker.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
Type case CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC to uint32_t
while defining sys_clock_hw_cycles_per_sec_runtime_get()
to extend the range of frequency to 0xffffffff.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
i.MX95 M7 is using multi-level interrupts with custom
interrupt handling. So, arm_custom_interrupt and
arm_irq_vector_table tests should exclude it.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Add some overlay files for the silabs xg29_rb4412a board to enable tests
on the board. Also add the platform to some testcase.yaml files.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Adds a test to verify Armv8.1-M MPU architecture's PXN attribute.
Verify PXN via static mpu config by utilizing existing __ramfunc MPU region
Since previous commit changes the behaviour of __ramfunc region,
executing userspace code in this region in privileged mode will
result in an MPU fault while execution in unprivileged mode should
work fine.
Verify PXN via DT by creating a custom section in the unused SRAM region.
Since the overlay sets the PXN attribute for the SRAM, executing code
in this region in privileged mode will result in an MPU fault while,
execution in unprivileged mode should work fine.
Also, instead of testing DT config for each board, do it only for MPS3
boards that which can be tested with simulation.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
What is the change?
- PXN attributes is set for static mpu regions such that
__ramfunc and __ram_text_reloc having userspace code
cannot be executed in privileged mode.
- Updated the notable change section to inform about the change in
behaviour of code executed from __ramfunc and __ram_text_reloc MPU
regions.
Why do we need this change?
- The current static MPU regions allows executing userspace/unprivileged
code from privileged mode which may not be expected and can lead to
secure privileged escalation attacks.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
Exclude RZ/A3UL SMARC board as the redefined CONFIG_SRAM_BASE_ADDRESS
degrades the BUILD_OUTPUT_ADJUST_LMA option that will generate a bin
file >10GB
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
This commit updates cortex_m related code to align it with the rules from
.clang-format. This is done to simplify future changes in these files as
we are about to implement use_switch support.
Some rules conflict with checkpatch and therefore some small part of the
code locally disable clang-format.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
test_arm_user_interrupt and test_arm_null_pointer_exception currently
only print "Skipped" but reports as PASS in twister. This fixes that
misleading report.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
This test uses the bellboard interrupts for the application
and the radio core builds on nRF54H20 and nRF9280.
Since it uses the bellboard interrupts it makes sense to ensure
that bellboard is disabled in device tree to avoid runtime issues.
This is preparation work, bellboard is planned to be enabled
by default later and this makes sure that the test will
continue to work.
Signed-off-by: Georgios Vasilakis <georgios.vasilakis@nordicsemi.no>
Mostly a revert of commit b1def7145f ("arch: deprecate `_current`").
This commit was part of PR #80716 whose initial purpose was about providing
an architecture specific optimization for _current. The actual deprecation
was sneaked in later on without proper discussion.
The Zephyr core always used _current before and that was fine. It is quite
prevalent as well and the alternative is proving rather verbose.
Furthermore, as a concept, the "current thread" is not something that is
necessarily architecture specific. Therefore the primary abstraction
should not carry the arch_ prefix.
Hence this revert.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Moves the arch_swap() declaration out of kernel_arch_interface.h
and into the various architectures' kernel_arch_func.h. This
permits the arch_swap() to be inlined on ARM, but extern'd on
the other architectures that still implement arch_swap().
Inlining this function on ARM has shown at least a +5% performance
boost according to the thread_metric benchmark on the disco_l475_iot1
board.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
CONFIG_ENTROPY_GENERATOR is now enabled by default as soon as
"zephyr,entropy" is set in the device-tree. Since the sub-Kconfig
CONFIG_ENTROPY_NRF5_RNG is also enabled by default on nrf boards,
this means that the driver is pulled in the build and intialized
at boot. This might cause runtime issues during some IRQ/kernel
tests, so it's better to remove "zephyr,entropy" on these tests.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
Convert them to native YAML lists. Support for space-separated
lists was deprecated in Twister a long time ago.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Disable the IPC communication between the domains
for the arm_thread_swap test since it is not needed
and it causes a flash oveflow for the no opmitization
test case.
Signed-off-by: Georgios Vasilakis <georgios.vasilakis@nordicsemi.no>
Introduce `CONFIG_RISCV_GP_PURPOSE` choice to make sure that only
one of `CONFIG_RISCV_GP` or `CONFIG_RISCV_CURRENT_VIA_GP` can be
enabled, instead of relying of dependencies.
To do that, introduce a new
`CONFIG_RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING` that can be selected
by SoC when it implemented global pointer (GP) initialization for
relative addressing in its linker.
`CONFIG_RISCV_GP` will be the default choice when
`CONFIG_RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING=y`
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Reset the the `gp` register to `_kernel->cpus[i].current` when
`CONFIG_USERSPACE` is enabled on exception to keep it sane.
Updated the testcase to test both `CONFIG_RISCV_GP` and
`CONFIG_RISCV_CURRENT_VIA_GP`.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
`_current` is now functionally equals to `arch_curr_thread()`, remove
its usage in-tree and deprecate it instead of removing it outright,
as it has been with us since forever.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
According to the RISC-V Instruction Set Manual: Volume II, Version 20240411
(Section 3.1.6.6), some implementations may choose to track the dirtiness
of the floating-point register state imprecisely by reporting the state to
be dirty even when it has not been modified. This option reflects that.
Also add a filter in `tests/arch/riscv/fpu_sharing/` based on imprecise
FPU state tracking
Signed-off-by: Jakub Wasilewski <jwasilewski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Changed interrupt priority for GPIO, default 6 is not suitable for
for the ZERO_LATENCY_IRQS function used in this test.
used in this test.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Add a test to make sure that the `gp` global pointer register used for
relative addressing when `CONFIG_RISCV_GP` is enabled can't be
corrupted by a rogue user thread.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
What is changed?
- Added a new mps3 board an552 for the soc corstone300.
The qualifier to build/run application with board mps3/an552 is
`mps3/corstone300/an552` for secure and
`mps3/corstone300/an552/ns` for non-secure.
- Added FVP variant to enable FVP testing with corstone300
and it uses the ARM FVP `FVP_Corstone_SSE-300_Ethos-U55`.
The qualifier to build/run application with FVP is
`mps3/corstone300/fvp` for secure and
`mps3/corstone300/fvp/ns` for non-secure.
- Note: the qualifier to build/run application with board mps3/an547
is now changed to
`mps3/corstone300/an547` for secure and
`mps3/corstone300/an547/ns` for non-secure.
How is it changed?
- Moved common code from mps3/an547 to corstone300.
- Renamed soc for an547 to corstone300 and added
a new soc corstone300/an552.
Why do we need this change?
- This enables FVP support and testing for corstone300.
- SOC/qualifier for mps3/an547 was renamed to reduce code redundancy
- A separate FVP variant was added for AN552 because, the TFM board
used for non-secure variant differs for FPGA and FVP.
TFM board `arm/mps3/corstone300/fvp` should be used when testing
AN552 with FVP and `arm/mps3/corstone300/an552` should be used when
testing with AN552 FPGA.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
We now use hwmv2 to list boards instead of relying on twister specific
config files.
One yaml files (twister.yaml for now) will have all the data needed for
all possible targets and variations of a board reusing most of the data
where possible and variations can override the top level data.
Twister keeps track of 'aliases' of boards and identifies that for
example native_sim is the same as native_sim/native, so either names
will be possible in both test yaml files or on the command line,
however, the reporting will always use the full name, so no there is no
confusion about what is being tested/built.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Apply the following changes to `nrf54h20dk` and `nrf9280pdk`:
* Convert `perm-*` properties to the newly introduced `nordic,access`,
both in board files and tests.
* Redefine shared regions to specify multiple access owners per node,
and ensure that each such region is reserved by one domain at a time.
`cpuapp_cpurad_ram0x_region` is only enabled by Radiocore, while
`cpuapp_cpucell_ram0x_region` is only enabled by Application core.
* Divide `shared_ram3x_region` so that each sub-region is owned by a
different domain. Their addresses must be rounded down to fit the
current UICR format.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Before commit baa70d8d36 ("arch/arm64/mmu: fix page table reference
counting part 2") it was possible to perform a partial unmap of a block
mapping. Restore that ability and provide a test case to validate it.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Having `CONFIG_EXCEPTION_STACK_TRACE_SYMTAB` to select the
`CONFIG_SYMTAB` or to explicitly not print the symbol name
during exception stack unwind seems unnecessary, as the extra
code to print the symbol name is negligible when compared with
the symbol table, so just remove it.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Currently it supports `esf` based unwinding only.
Then, update the exception stack unwinding to use
`arch_stack_walk()`, and update the Kconfigs & testcase
accordingly.
Also, `EXCEPTION_STACK_TRACE_MAX_FRAMES` is unused and
made redundant after this change, so remove it.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Currently it supports `esf` based unwinding only.
Then, update the exception stack unwinding to use
`arch_stack_walk()`, and update the Kconfigs & testcase
accordingly.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
qemu_riscv32e uses a different ISA and is kinda special, add it
to the testcase for better coverage.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
The symtab test should have the
`CONFIG_EXCEPTION_STACK_TRACE_SYMTAB` enabled. This was not
caught in the CI previously as the regex was also wrong, '['
and ']' are regex syntax and should be escaped.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Fix preprocessor expression for custom vector table due
to OS timer isr being needed. The parentheses are missing.
Also add RW6xx to the list which has the same isr needed for ostimer.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The Renesas RA ICU forcibly enables GEN_ISR_TABLES, and it remains
enabled even if it is disabled in prj.conf.
Adding `not CONFIG_GEN_ISR_TABLES` to the filter condition to skip
this case.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Created the `arch_stack_walk()` function out from the original
`z_riscv_unwind_stack()`, it's been updated to support
unwinding any thread.
Updated the stack_unwind test case accordingly.
Increased the delay in `test_fatal_on_smp`, to wait
for the the fatal thread to be terminated, as stacktrace can
take a bit more time.
Doubled the kernel/smp testcase timeout from 60 (default) to
120s, as some of the tests can take a little bit more than 60s
to finish.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
This code was never formally tested before... and without the preceding
commit it obviously didn't work either.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Renames:
Z_KERNEL_VIRT_START to K_MEM_KERNEL_VIRT_START
Z_KERNEL_VIRT_SIZE to K_MEM_KERNEL_VIRT_SIZE
Z_KERNEL_VIRT_END to K_MEM_KERNEL_VIRT_END
This is part of a series to move memory management related
stuff from Z_ namespace into its own namespace.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Renames:
Z_PHYS_RAM_START to K_MEM_PHYS_RAM_START
Z_PHYS_RAM_SIZE to K_MEM_PHYS_RAM_SIZE
Z_PHYS_RAM_END to K_MEM_PHYS_RAM_END
This is part of a series to move memory management related
stuff from Z_ namespace into its own namespace.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Make `struct arch_esf` compulsory for all architectures by
declaring it in the `arch_interface.h` header.
After this commit, the named struct `z_arch_esf_t` is only used
internally to generate offsets, and is slated to be removed
from the `arch_interface.h` header in the future.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
