Increase stack size for test thread. With no optimization
default stack size may not be enough.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
This commit enables the assert test mode (`CONFIG_ASSERT_TEST`) for the
ARM interrupt test because it relies on the assert function to return
without aborting in the "Assert occurring inside kernel panic" test.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit enables the assert test mode (`CONFIG_ASSERT_TEST`) for the
ARM interrupt test because it relies on the assert function to return
without aborting in the in-ISR "Intentional assert" test.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
If the test is run with the config NO_OPTIMIZATIONS enabled then the
stack size usage increases by around 80% for ARM platforms.
Increase the stack size used in test cases that enables building with no
optimizations for ARM.
Update description on TEST_ARM_CORTEX_M since it was outdated and said
it was only used for a single purpose.
Fixes: #47930Fixes: #47929Fixes: #47855
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Add a bunch of missing "zephyr/" prefixes to #include statements in
various test and test framework files.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
irq_lock() returns an unsigned integer key.
Generated by spatch using semantic patch
scripts/coccinelle/irq_lock.cocci
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
The test fails on several stm32 platforms, due to the
correlation between test_arm_syscalls and
test_arm_thread_swap, so disable the corresponding IRQ
interrupt may fix it.
Signed-off-by: Shaoan Li <shaoanx.li@intel.com>
This test has been bitrotting for a while - years, in fact. As it didn't
have a `testcase.yaml`, it wasn't being run on twister. The code expects
to be run on single thread environment, but xtensa arch currently
doesn't support that.
This patch simply removes this test - if it's deemed important, it can
be reworked and readded in the future.
Fixes#47508.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Move the direct interrupt test to tests/arch/x86/direct_isr. Two
reasons:
1. The direct interrupt is only for x86. It's arch-specific.
2. And it need extra gcc option to pass the build, that will
include testsuite number. Although it seems like we add a
extra testsuite for it, actually we can reduce whole tests
configuration in tests/kernel/interrupt. And also make this
test more generic as it used to be.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
Following implementation of commit 219d5b5,
and to complement commit 8c4f98d
it is also necessary define _vector_end in
test specific arm-irq-vector-table.ld
Fixes#47273
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Disabling nucleo_l552ze_q_ns from the test suite since there isn't
enough room to sign the image with the toolchain used in CI. This can
be reverted if changes are made to the nucleo_l552ze_q_ns platform to
enable enough room for the signing data.
Signed-off-by: Kevin Townsend <kevin.townsend@linaro.org>
Picolibc enables TLS, which causes relocation errors with some of these
tests without changing the compiler code model.
Signed-off-by: Keith Packard <keithp@keithp.com>
As Zephyr currently requires CMake version 3.20.0, update all
occurrences of cmake_minimum_required.
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
This test is based on the wrong assumption that the IRQ vector table
symbols are always placed by the linker script also when
CONFIG_GEN_IRQ_VECTOR_TABLE is not actually set.
This is of course broken with the reworked mechanism of the IRQ vector
table placement.
Fix the test by reintroducing the old behaviour by forcefully
reinstating the symbols in the linker script.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
On mcu with Data Cache, when it is enabled (CONFIG_DCACHE=y),
the DCACHE must be flushed after the NMI loop to trig all
the irq, else the last one is missing.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit corrects all `extern K_THREAD_STACK_DEFINE` macro usages
to use the `K_THREAD_STACK_DECLARE` macro instead.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
to NOT_SET, in case the default is changed.
Add print of failing error code for psa_hash_compute().
Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
Adds few missing zephyr/ prefixes to leftover #include statements that
either got added recently or were using double quote format.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Update the new API to use K_USER as the flags for both
CONFIG_USERSPACE and CONFIG_TEST_USERSPACE. Also, fix the linker
script to properly include the suites, tests, and rules.
Fixes#44108
Signed-off-by: Yuval Peress <peress@google.com>
Instead of relying on runtime filter to limit scope to emulation
platforms, use the type attribute for each platform and do the filtering
very early on. This will speed things up for tests where we only run on
emulation platforms.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add the ability to have multiple irq priority levels which are not
masked by irq_lock() by adding CONFIG_ZERO_LATENCY_LEVELS.
If CONFIG_ZERO_LATENCY_LEVELS is set to a value > 1 then multiple zero
latency irqs are reserved by the kernel (and not only one). The priority
of the zero-latency interrupt can be configured by IRQ_CONNECT.
To be backwards compatible the prio argument in IRQ_CONNECT is still
ignored and the target prio set to zero if CONFIG_ZERO_LATENCY_LEVELS
is 1 (default).
Implements #45276
Signed-off-by: Christoph Coenen <ccoenen@baumer.com>
The goal of this commit is to update existing STM32 boards descriptions
to use these size "DT_SIZE" macros to enhance readability. To realize this
i used a python script, which will detect the STM32 Boards
/zephyr/board/arm, and then will update in the dts files the partition
description using "DT_SIZE_K" and "DT_SIZE_M" macros.
Check manually and modify in .overlay files in samples and tests.
Signed-off-by: TLIG Dhaou <dhaou.tlig-ext@st.com>
Assembler files were not migrated with the new <zephyr/...> prefix.
Note that the conversion has been scripted, refer to #45388 for more
details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In order to bring consistency in-tree, migrate all tests to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
There are boards without CMOS RTC, where blind accesses to
the RTC registers will freeze the system. So make the test
works with these boards if CONFIG_COUNTER_CMOS=n.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
With GCC 11 now supporting low overhead branching in ARMv8.1, ASM "LE"
(loop-end) instructions would trigger an INVSTATE hard-fault after
FPSCR was set to 0. This was due to the FPSCR getting a new field in
ARMv8.1. LTPSIZE is now set to it's reset value of Tail predication not
applied.
Signed-off-by: Ryan McClelland <ryanmcclelland@fb.com>
