* New m_can driver variant for STM32H7, as it uses the complete m_can
register set.
* Fix definitions for CAN_MCAN_RXF0S_F0FL, CAN_MCAN_TXEFC_EFSA_POS.
Signed-off-by: Jeremy Wood <jeremy@bcdevices.com>
The irq_lock() API is a legacy API not to be used for synchronization
by new code, and in any case is only being used in cargo-cult fashion
here. These test cases all do synchronous exceptions, there's
literally nothing to synchronize against.
(And in this case they're exposing a legacy wart. On platforms where:
1. SMP=y, which causes irq_lock() to be implemented as a somewhat
complicated global lock
2. No ARCH_EXCEPT() macro is defined, which causes the kernel to
use a fallback that simply aborts the current thread.
...this test will then abort a thread holding the lock, which will
cause it to be orphaned (if it weren't a legacy API, the kernel
should probably attempt to clean it up in k_thread_abort(), but it
is, and it doesn't), so the next attempt to lock it will hang.
And it's even worse, because this test builds with SMP=y and
MP_NUM_CPUS=1, so the hand will happen with interrupts masked on a
system with only one CPU, and everything will lock up solid.)
Fixes#41877
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Update the custom vector table to add the OS Event timer
interrupt which is used on RT595 as the kernel system timer
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
1. Update to add support for Flexcomm8-13.
2. Fix the clock control driver, the enclosing #define
was incorrect.
3. Identify HS_SPI port using the appropriate Register
define
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
For multicore devices like nRF53, shim layer part of setting mac keys
and frame counters is called on application core where
CONFIG_NRF_802154_ENCRYPTION is disabled (the define concerns radio
driver for net core). This commit replaces
CONFIG_NRF_802154_ENCRYPTION with CONFIG_IEEE802154_2015.
Signed-off-by: Lukasz Maciejonczyk <lukasz.maciejonczyk@nordicsemi.no>
Implement an empty `otPlatLog` function when `CONFIG_LOG` is not
enabled. This also fixes the issue with `log_count_args` not being
available when logging is disabled.
Signed-off-by: Eduardo Montoya <eduardo.montoya@nordicsemi.no>
DMA between a host os and processor (such as an x86 processor running
linux) and vice versa is used and supported by Intel's HDA DMA
Controller. This provides a method to transfer data, using hardware,
between the host and the local processor running Zephyr. The enums
added here are used to extend the dma_status direction enum
which provides information back to the DMA user and driver the
direction of the DMA transfer for a particular channel. This can
then be used, where needed, to add logic around the direction of the
transfer.
In addition to adding the two directions it adds enums to account for
cases where additional DMA directions that are IP and driver specific
may exist.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
We don't use TLB at the moment. Jumping to address 0 (USEG)
leads to TLB exception (instruction fetch).
Division by zero leads to TRAP exception.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
The MIPS Malta is an ATX form factor evaluation board made by MIPS
Technologies. Malta board is the most popular platform for MIPS
full-system emulation.
See https://www.linux-mips.org/wiki/MIPS_Malta for details.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
The MIPS Malta is an ATX form factor evaluation board made by MIPS
Technologies. Malta board is the most popular platform for MIPS
full-system emulation.
See https://www.linux-mips.org/wiki/MIPS_Malta for details.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Remy Luisant <remy@luisant.ca>
This commit adds support for tickless operation on the MIPS CP0 timer.
The code closely follows the Xtensa and RISCV timer drivers.
All tests pass.
Signed-off-by: Remy Luisant <remy@luisant.ca>
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
This commit defines the toolchain command line options for the
Zephyr MIPS architectural port.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Remy Luisant <remy@luisant.ca>
MIPS (Microprocessor without Interlocked Pipelined Stages) is a
instruction set architecture (ISA) developed by MIPS Computer
Systems, now MIPS Technologies.
This commit provides MIPS architecture support to Zephyr. It is
compatible with the MIPS32 Release 1 specification.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Skip re-initialization of statically initialized PDU struct
fields that are not modified at runtime.
When supporting connection oriented CTE, the cp bit and
resv field used for CTE info are modified, hence
re-initialized these and accordingly reset the values
when just-in-time HCI Tx Data fragmentation is performed
in the Lower Link Layer.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
In order to preserve stack, this replaces the single-bus enumeration
loop by a stack based non-recursive pcie hierarchy iteration.
Each stack entry contains a bridge bus enumeration state.
When a bridge endpoint is detected on the current bus, it is
configured and this new bus is pushed on top of the stack in
order to be enumerated at next loop.
When enumeration ends on the bus, the current bus state is
removed from the stack to continue enumeration on the previous
bus.
This enumeration affects a sequential bus number to each new
bus detected in the same order as Linux & U-Boot does.
In this hierarchy:
[0 1 2 ... 31]
| | |
EP | |
| |
[0 1 ... 31] [0 ... 31]
| | |
| EP |
| [0 ... 31]
[0 ... 31] |
| EP
EP
We will get the following BDFs enumeration order:
00:00.0 Endpoint
00:01.0 Bridge => Bus primary 0 secondary 1
01:00.0 Bridge => Bus primary 1 secondary 2
02:00.0 Endpoint
... Bus secondary 2 => subordinate 2
01:01.0 Endpoint
... Bus secondary 1 => subordinate 2
00:02.0 Bridge => Bus primary 0 secondary 3
03:00.0 Bridge => Bus primary 3 secondary 4
04:00.0 Endpoint
... Bus secondary 4 => subordinate 4
... Bus secondary 3 => subordinate 4
The gives the following primary/secondary/subordinate map:
Bus 0 [0 1 2 ... 31]
| | |
| [0:1->2] [0:3->4]
EP 00:00.0 | |
| |
Bus 1 [0 1 ... 31] Bus 3 [0 ... 31]
| | |
| EP 01:01.0 |
[1:2->2] [3:4->4]
| |
| Bus 4 [0 ... 31]
Bus 2 [0 ... 31] |
| EP 04:00.0
EP 02:00.0
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This adds setup of Type 1 bridge endpoints in two steps, first when
endpoint is detected and secondly when enumerating the next endpoint.
First, the code configures the bus primary & secondary number and 0xff
as subordinate to redirect all PCIe messages to this bus.
Then memory & I/O base are programmed by getting the current allocation
bases.
Finally, now right away, we program the subordinate to the max bus
number under the bridge, here the same, and the memory & I/O limit,
here lower than the base.
This doesn't make the bridge totally usable, enumeration would work
bus not for nested bridges and BARs wouldn't be accessible.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
In order to prepare support for bridges enumeration, split out the
actual endpoint enumeration code out of the enumeration loop.
Pass a skip_next_func boolean to indicate if the current endpoint
is multifunction of not, to continue to next dev or next function.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The Type 1 endpoints has 2 BARs are the same position as the Type 0
BARS 0 & 1, so reuse the generic_pcie_ctrl_type0_enumerate_bars()
for both types by passing the number of possible BARs on the endpoint.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
When enumerating bridges, the allocated memory base and limit must be
programmed in the bridge config registers.
The base is programmed when starting enumerating the bridge and the
limit is programmed when all endpoints of the bridge and sub-bridges
are enumerated.
Add a second callback to get the base of the next allocation in
order to fill these base & limit values.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
When a device returns -ENOTSUP for actions TURN_ON or TURN_OFF
the device state still has to be updated since the domain will
cut or restore the energy.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Add an initial demonstration of a physical power domain running on the
`qemu_cortex_m3` platform.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Initial implementation of a simple GPIO controlled power domain.
It exposes no API of its own, all functionality is contained inside
the runtime power management callbacks.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Add a function to tell runtime power management that the device is
starting in the off state instead of active or suspended.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Adds a helper for devices to check if they are on a power-domain or not.
Drivers can use this information to determine if they will be turned on
at some point in the future, or if they are already turned on.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
