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59608 commits

Author SHA1 Message Date
Gerard Marull-Paretas
e5e73a70e9 soc: remove unnecessary inclusions of devicetree.h
Many ARM SoCs included <devicetree.h> likely due to:

1. nvic.h not being self-contained
2. As a result of copy-paste

Some RISC-V SoCs had the same problem, in this case likely due to
copy-paste from ARM. The <devicetree.h> header has been removed using
the following command:

sed -i ':a;N;$!ba;s/#include <devicetree\.h>\n//g' soc/**/soc.h

soc.h files that make a legitimate usage of the API have not been
changed.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 11:52:27 +01:00
Gerard Marull-Paretas
a84a16f8ff arch: arm: aarch32: cortex_m: nvic: make header self-contained
The header contains macros that make use of the Devicetree API, however,
<devicetree.h> is not included. This was "mitigated" by most <soc.h>
including <devicetree.h>.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 11:52:27 +01:00
Gerard Marull-Paretas
31ad52336b soc: riscv: telink_b91: fix required headers
The linker script is using the DT API, which was previously included via
<soc.h>.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 11:52:27 +01:00
Gerard Marull-Paretas
130b06a0fd soc: riscv: riscv-privilege: andes_v5: make smu.h self contained
The header was not self-contained: it uses DT and utility macros but
<devicetree.h> and <sys/util_macro.h> were not included.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 11:52:27 +01:00
Gerard Marull-Paretas
a08e87e078 soc: arm: silabs_exx32: make soc_pinmap.h self contained
The soc_pinmap.h uses the DT API, so these headers needs to include
<devicetree.h>.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 11:52:27 +01:00
Gerard Marull-Paretas
7a5ee28755 soc: arm: atmel_sam0: common: soc_port: add missing include
The source file uses boolean types internally, however, <stdbool.h> was
not included. It was likely included indirectly before via
<devicetree.h> -> <sys/util.h>.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 11:52:27 +01:00
Gerard Marull-Paretas
095a21e2cf soc: arm: nuvoton_npcx: make soc_*.h headers self-contained
Almost none of the soc_*.h headers were self-contained. This patch adds
all necessary includes to improve the situation.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 11:52:27 +01:00
Tim Lin
96203820db boards: it8xxx2_evb: add aliases of i2c0
Add the aliases, we are able to build test of
tests/drivers/i2c/i2c_api for the it8xxx2_evb board.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2022-01-11 11:51:04 +01:00
Tim Lin
d676b51485 ITE: drivers/i2c: add the API of get configuration
This commit adds the API of get_config that will make test of
tests/drivers/i2c/i2c_api pass on it8xxx2_evb board.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2022-01-11 11:51:04 +01:00
Marius Scholtz
14e15df00f drivers: arm: stm32: adc: Added Shared IRQ
Certain stm32 soc's have a single shared irq for all adc channels
on those soc's only a single channel is supported.

Added a Kconfig that enables a shared irq for stm32f2x, stm32f4x,
stm32f7x soc's. The shared IRQ uses a flag to limit the number of
interrupts defined to only 1. A shared irq handler is added which
determines which ADC instance the interrupt is for, it then calls
into the existing interrupt.

Signed-off-by: Marius Scholtz <mariuss@ricelectronics.com>
2022-01-11 11:50:43 +01:00
Gerard Marull-Paretas
412c051fbf codeowners: add GD32 RISC-V boards
Add myself as a code owner for GD32 RISC-V boards.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-01-11 11:50:35 +01:00
Gerard Marull-Paretas
5523528144 maintainers: add GD32 RISC-V boards to GD32 Platforms
Add RISC-V GD32 official boards (e.g. gd32vf103v_eval) to the file list
in the GD32 Platforms section.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-01-11 11:50:35 +01:00
Gerard Marull-Paretas
97cc216957 tests: drivers: gpio: gpio_basic_api: add support for gd32vf103v_eval
Add DT overlay to run gpio_basic_api test on GD32VF103V-EVAL board. In
order to make testing easy a couple of accessible pins have been
selected: PD0 and PD1 pins exposed via JP13 and JP4 respectively.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-01-11 11:50:35 +01:00
Gerard Marull-Paretas
a4790bcfab boards: riscv: gd32vf103v_eval: initial support
Add initial support for the GD32VF103V-EVAL board. The board is based on
the GD32VF103 RISC-V MCU.

This board can run on Zephyr now largerly thanks to the initial work
done by @soburi.

Note that this board requires using the riscv-openocd fork, however,
programming is slow when using OpenOCD even though it works (including
debugging). J-Link option has also been enabled as it seems to be more
realiable and works _out of the box_. Some details are given in the
board documentation file.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-01-11 11:50:35 +01:00
Gerard Marull-Paretas
1e81e7cded drivers: pwm: gd32: enable gd32vf103
Add dependency on SOC_SERIES_GD32VF103. The driver is compatible as is
with this series.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-01-11 11:50:35 +01:00
Gerard Marull-Paretas
c8a630ab77 dts: riscv: gigadevice: gd32vf103: add timers and pwm
Add entries for timers and PWM devices.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-01-11 11:50:35 +01:00
Gerard Marull-Paretas
cdcd11aac0 drivers: gpio: gd32: enable gd32vf103
The device implemented by this driver is also available on GD32 RISC-V
MCUs.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-01-11 11:50:35 +01:00
Gerard Marull-Paretas
ddf440fe60 dts: riscv: gigadevice: gd32vf103: include GPIO bindings
Include the GPIO dt-bindings header (required for gpio cells).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-01-11 11:50:35 +01:00
Gerard Marull-Paretas
c4269ba947 drivers: interrupt_controller: gd32_exti: enable gd32vf103
The device implemented by this driver is also available on GD32 RISC-V
MCUs.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-01-11 11:50:35 +01:00
Gerard Marull-Paretas
806f5de18d dts: riscv: gigadevice: gd32vf103: add exti
Add EXTI node, required by the EXTI and GPIO drivers.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-01-11 11:50:35 +01:00
Gerard Marull-Paretas
07eee1bc79 drivers: interrupt_controller: gd32_exti: isr may be unused
The gd32_exti_isr function may be unused if the GPIO driver is not
enabled but EXTI is (no IRQ will connect to it). This may be improved in
the future by requiring explicit enablement of the exti DT node.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-01-11 11:50:35 +01:00
Emil Gydesen
43b827c562 zephyr: Add UTF8 kconfig to conditionally compile utf8.c
Add the kconfig option so that the utf8.c file can be
conditionally compile, and only for the applications
that need it.

Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
2022-01-11 11:50:15 +01:00
Emil Gydesen
baf48fbe2e zephyr: Add UTF-8 truncating strlcpy variant
Add a function to copy a UTF-8 encoded string that
ensure correct truncation of the string if the source
is larger than the destination, as well as ensuring that
the resulting destination string is NULL-terminated.

Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
2022-01-11 11:50:15 +01:00
Emil Gydesen
5cb72d2193 zephyr: Add function to properly truncate UTF-8 strings
Add a function that can properly truncate UTF-8 strings
without leaving unterminated started characters,
as UTF-8 characters can be 1-4 bytes long.

Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
2022-01-11 11:50:15 +01:00
Shao Ming
7e318b5e93 soc/intel_adsp: Fix the PFN width in cavs-fw.py loader
Change the PFN field width from 54 to 55 to follow the Linux Doc.
(https://www.kernel.org/doc/html/latest/admin-guide/mm/pagemap.html)
Otherwise issue may arise if physical address beyond 2^66 is mapped.

Refactor the v15 and v25 scripts to extract the common part.
This is to suppress the pylint duplicate code check.

Signed-off-by: Shao Ming <ming.shao@intel.com>
2022-01-11 11:49:53 +01:00
Francois Ramu
0434c1fcb8 tests: drivers: uart async on stm32h743 nucleo board
connect USART2 D53 / TX (pd5) to D52 / RX (pd6)
on the ARDuino connector CN9 of the nucleo board

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-01-11 11:49:23 +01:00
Tim Lin
45b6aa4c3b ITE: drivers/i2c: add the compatibility of GPIO F2/F3 for i2c3
The default I2C channel 3 is used by alternate function of GPIO H1/H2
Krabby uses GPIO F2/F3 as I2C channel 3, so we need to add the
compatibility of the GPIO F2/F3.

TEST=test on it8xxx2_evb:
zmake configure -b zephyr/projects/it8xxx2_evb/

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2022-01-11 11:49:16 +01:00
Jaremy J. Creechley
3ac2ca2aa5 net: socket: extend posix compatability SO_<opts>
Adding these definitions help ease of porting POSIX applications.

They currently do nothing in the core network stack and will
return an error if used. However, they help port some POSIX
without changing these. In particular, this enables using the
Nim programming language's standard library with Zephyr.

- The values copy Linux amd64, similar to the other SO_OPTIONS
- Add SO_SNDBUF to fix simplelink wifi
- Use compat options in simplelink wifi

Signed-off-by: Jaremy J. Creechley <jaremy.creechley@panthalassa.com>
2022-01-11 11:48:16 +01:00
Dominik Ermel
bd10559364 mgmt/mcumgr/lib: Shorten error path in taskstat processing
The tasktat code filling reposes with use of CBOR has been modified,
utilizing lazy evaluation of C '||' operator, to terminate CBOR
encoding as soon as first error appears.

Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
2022-01-11 11:48:08 +01:00
Dominik Ermel
78f01b5900 mgmt/mcumgr/lib: Add OS_MGMT_TASKSTAT_STACK_INFO to mcumgr
The commit adds OS_MGMT_TASKSTAT_STACK_INFO Kconfig option
that allows to skip, when disabled,  "stksz" and "stkuse" reports,
in "taskstat" command responses.

Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
2022-01-11 11:48:08 +01:00
Dominik Ermel
a566c92c1c mgmt/mcumgr/lib: Thread name selection for taskstat report
The commit adds Kconfig options and supporting code that allows
to select characteristic that will be used for thread name
in taskstat from:
 - thread name, when THREAD_NAME is enabled;
 - thread ID/index;
 - thread priority.

Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
2022-01-11 11:48:08 +01:00
Dominik Ermel
49a3624cc8 mgmt/mcumgr/lib: Allow signed priorities in taskstat
By default the mcumgr taskstat responses send task priorities
as unsigned integers, while Zephyr uses int8_t as priority type.
This commit adds OS_MGMT_TASKSTAT_SIGNED_PRIORITY Kconfig option
that allows to switch to use signed priorities in responses.

Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
2022-01-11 11:48:08 +01:00
Dominik Ermel
e293be6ab0 mgmt/mcumgr/lib: Make thread name in taskstat response configurable
The change adds OS_MGMT_THREAD_NAME_LEN that allows to set length of
thread name that is returned in taskstat response.

Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
2022-01-11 11:48:08 +01:00
Dominik Ermel
845010287a mgmt/mcumgr/lib: Optimize taskstat for Zephyr
The commit changes taskstat code to directly process thread information
from Zephyr structures, instead of translating them to system agnostic
layer, before formatting response.
It also moves the takstat code to os_mgmt.c.

Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
2022-01-11 11:48:08 +01:00
Dominik Ermel
e6437a7ef3 mgmt/mcumgr/lib: Remove os_mgmt_config.h
The commit removes os_mgmt_config.h that has been translating Kconfig
options to mgmt internal definitions for constants, and replaces
usage of these constants with direct use of Kconfig options.

Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
2022-01-11 11:48:08 +01:00
Jonathan Hahn
236aeadd4f samples: uart: Add sample for single line uart
The sample uses st single-line uart mode on stm32 boards.

Signed-off-by: Jonathan Hahn <Jonathan.Hahn@t-online.de>
2022-01-11 11:47:47 +01:00
Jonathan Hahn
32f9dcf328 drivers: uart: Add support for st single wire mode
An additional devicetree poperty `single-wire` is added
to uart and usart bindings of stm32. The driver checks this value
during initialization and enables the single wire mode when set.

Signed-off-by: Jonathan Hahn <Jonathan.Hahn@t-online.de>
2022-01-11 11:47:47 +01:00
Yuval Peress
ab1caef8c3 ztest: Update ztest with more powerful testing APIs
1. Test suites in prior ztest serve no purpose other than logical
ordering of tests into a named-group. Move the construct of setup and
teardown into the test suite and away from individual tests.
Additionally, add the constructs of before/after to the test suites.
This model more closely resembels other testing frameworks such as gTest
and Junit.
2. Test can be added to a suite by using ZTEST() or ZTEST_F() where _F
stands for fixture. In the case where _F is used, the argument `this`
will be provided with the type `struct suite_name##_fixture*`. Again,
this models other modern testing frameworks and allows the test to
directly access the already set up data related to the test suite.
3. Add the concept of test rules (from Junit). Rules are similar to the
before/after functions of the test suites but are global and run on all
suites. An example of a test rule can be to check that nothing was
logged to ERROR. The rule can cause the test to fail if anything was
logged to ERROR during an integration test. Another example would be a
rule that verifies that tests ran within some defined timeout.

Signed-off-by: Yuval Peress <peress@google.com>
2022-01-11 11:47:30 +01:00
Jim Shu
74faa18902 soc: riscv: virt: enable RISC-V PMP support
Enable CONFIG_RISCV_PMP in qemu virt soc. Use this SoC as CI testing
platform of RISC-V PMP and Userspace.

Signed-off-by: Jim Shu <cwshu@andestech.com>
2022-01-11 11:47:03 +01:00
Jim Shu
76c8c6ed79 arch: riscv: pmp: add PMP protection of code and rodata
This commit enable PMP-based memory protection of code and rodata
instead of relying on non-writable real HW (e.g. flash). Use static
PMP region with PMP Lock bit to protect them in both user/supervisor
mode.

Signed-off-by: Jim Shu <cwshu@andestech.com>
2022-01-11 11:47:03 +01:00
Jim Shu
df166ddda1 arch: riscv: pmp: change mechanism of arch_buffer_validate()
Implement new mechanism of arch_buffer_validate() to support checking
static PMP regions. This is preparation patch for code/rodate protection
via RISC-V PMP.

Signed-off-by: Jim Shu <cwshu@andestech.com>
2022-01-11 11:47:03 +01:00
Jim Shu
35ef71f7c0 arch: riscv: pmp: simplify thread initialization
Thread init related to PMP & userspace contains 5 parts:

1. User/supervisor thread clear PMP context
2. User thread clear it's context
3. User/supervisor thread assign to different entry
4. Supervisor thread assign mstatus.MPRV for M-mode PMP protection
5. User/supervisor thread setup PMP regions of stack guard if enabled

Signed-off-by: Jim Shu <cwshu@andestech.com>
2022-01-11 11:47:03 +01:00
Jim Shu
9683c9e71c arch: riscv: pmp: reorder function definitions
Reorder the memory domain async functions to:
  arch_mem_domain_partition_add()
  arch_mem_domain_partition_remove()
  arch_mem_domain_thread_add()
  arch_mem_domain_thread_remove()

Signed-off-by: Jim Shu <cwshu@andestech.com>
2022-01-11 11:47:03 +01:00
Jim Shu
b13dd54fb4 arch: riscv: pmp: simplify pmp region number computation
Simplify multiple ifdef case in computing region number. Also move these
macros to core_pmp.c because they are only used in one file.

Signed-off-by: Jim Shu <cwshu@andestech.com>
2022-01-11 11:47:03 +01:00
Jim Shu
e3c8b4cae4 arch: riscv: pmp: introduce riscv_pmp_region structure
Using struct riscv_pmp_region to modulize PMP CSR handling, including
PMP NAPOT/TOR mode handling. This patch can make us more easily to
add/remove RISC-V PMP regions without considering register handling.

Signed-off-by: Jim Shu <cwshu@andestech.com>
2022-01-11 11:47:03 +01:00
Jim Shu
e4c5d96a8b arch: riscv: pmp: enable MPU log module for debugging
Cleanup logging API in core_pmp.c. Remove old printf-based debugging API
and change the log module of PMP to individual MPU log module.

Signed-off-by: Jim Shu <cwshu@andestech.com>
2022-01-11 11:47:03 +01:00
Jim Shu
5fc5beabe2 arch: riscv: pmp: fix IRQ handling of PMP stack guard
This commit add 2 minor fixes of IRQ handling:

1. Save caller registers before calling z_riscv_configure_stack_guard()
in RISC-V assembly.

2. reschedule and no_reschdule code paths use different interrupt
return path after supporting of CONFIG_PMP_STACK_GUARD. back-to-back
interrupt checking is in the reschedule code path so that it should
jump to interrupt return path of reschedule.

Signed-off-by: Jim Shu <cwshu09@gmail.com>
2022-01-11 11:47:03 +01:00
Jim Shu
5a93c74ba3 tests: disable division-by-zero test in RISC-V arch
Because RISC-V arch (M extension) doesn't trigger exception for
division-by-zero, this test can't support RISC-V and is disabled in
RISC-V.

Signed-off-by: Jim Shu <cwshu@andestech.com>
2022-01-11 11:47:03 +01:00
Jim Shu
e0329a5525 arch: riscv: pmp: fix return value of arch_mem_domain_partition_remove()
If no thread use this memory domain, there isn't any user PMP region
translated from memory partitions in domain. In this case, memory
partition removal doesn't need to remove user PMP region and
arch_mem_domain_partition_remove() could just successfully return.

Signed-off-by: Jim Shu <cwshu@andestech.com>
2022-01-11 11:47:03 +01:00
Jim Shu
fd1e5aebc0 arch: riscv: fix sp of supervisor thread in _Fault function.
Although CONFIG_USERSPACE is enabled, there are supervisor threads who
don't have privileged stack using exception handler. Only let user
threads to switch to privileged stack in exception handler.

Signed-off-by: Jim Shu <cwshu@andestech.com>
2022-01-11 11:47:03 +01:00