This is defining the SYS_CLOCK_TICKS_PER_SEC default value
depending on the LPTIM CLOCK frequency in case of LPTIMER,
to get a TICK value as a divider of the LPTIM clock source.
It gives a better result in formulas when converting
ticks to count unit.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This adds a helper function for reading LiteX 64-bit CSRs
to be used by LiteX drivers.
Signed-off-by: Jakub Cebulski <jcebulski@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
emsdp is a FPGA based platform, can be loaded with different
configurations. Different configuration have different
interrupts:
* em5d, em7d and em11d have 111 interrupts
* em4 and em6 have 113 interrupts
* em7d_esp has 112 interrupts
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
UARTs and I2C controllers are accessed through MMIO and
these regions need to be added to MMU for proper access.
This also enable MMU for Apollo Lake by default since
serial console is now usable.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This file consists only of an array of per-CPU IOAPIC ID's that
overrides the weak symbol defined by the architecture.
The IOAPIC IDs are only used when targetting a startup IPI for the
auxiliary right now, but the IDs are the IDs and represent hardware
truth. They should be correct even if unused.
Using the wrong ones also breaks the tests/kernel/mp test, which calls
arch_start_cpu() when not in SMP mode as a deliberate unit test.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The APIC timer is not supported e.g. with SMP (which will be enabled
by default soon as well) so the sensible choice is to default to HPET.
Also, the default makes more sense to be on the SoC side, so move it
there from the board defaults.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The nodelabel references for the GPIO region MMU setup were incorrect.
The nodelabel names didn't match what is in the dts. Fix this otherwise
we get a compile error when enabling the functionality.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Several reviewers agreed that DT_HAS_NODE_STATUS_OKAY(...) was an
undesirable API for the following reasons:
- it's inconsistent with the rest of the DT_NODE_HAS_FOO names
- DT_NODE_HAS_FOO_BAR_BAZ(node) was agreed upon as a shorthand
for macros which are equivalent to
DT_NODE_HAS_FOO(node) && DT_NODE_HAS_BAR(node) &&
- DT_NODE_HAS_BAZ(node), and DT_HAS_NODE_STATUS_OKAY is an odd duck
- DT_NODE_HAS_STATUS(..., okay) was viewed as more readable anyway
- it is seen as a somewhat aesthetically challenged name
Replace all users with DT_NODE_HAS_STATUS(..., okay), which is
semantically equivalent.
This is mostly done with sed, but a few remaining cases were done by
hand, along with whitespace, docs, and comment changes. These special
cases include the Nordic SOC static assert files.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The Atmel SAM D21 SoC, according to the original Atmel datasheet
(Atmel-42181N), has 28 interrupt lines (0-27).
There have been mysterious changes in the number of interrupt lines and
on-chip peripherals in the recent Microchip datasheet releases, but
there is no explicit information available for this (e.g. PCN), so we
take the safest approach by assuming the lowest interrupt line number.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Make it possible for an application to set CONFIG_I2C=n if it wants.
The unconditional select was making this impossible due to resulting
unmet dependencies.
This is also in line with what some other SoC definitions do with I2C.
Fixes#25204
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
PSA level 1 requires secure boot. TF-M BL2 is the official
secure boot loader. It needs a BL2_HEADER_SIZE offset.
Align nonsecure address with TF-M's NS slot while TF-M BL2 enabled.
Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
Add infineon XMC4 series UART support. Driver supports
only poll mode using XMCLib.
Out of 4 available UART's on SoC, only UART1 is confgired
by default in UART mode until GPIO & pinctrl support.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Add infineon xmc series with XMC4500 support. XMC series comes with,
- CPU operates upto 120MHz
- 3 RAM (PSRAM1 - code, DSRAM1 - data and DSRAM2 - communiation)
- upto 1MB flash
init: clock control & gpio is not done, so SoC initialization directly
relies on HAL. Core operating clock is stored in no_init section, which
is kept under DSRAM1. Only DSRAM1 is used until clock support. Using
PSRAM1 and DSRAM1 needs adaptation in linker script - planned for next
revision.
Note: SystemInit cannot be consumed directly due to vector table +
HAL linker dependency.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Add initilizations for:
- Cortex-A72 L2 Controller configurations. This initialization to
be done when cluster is in quiscent state.
- 'ICC_SRE_EL3' init to allow GIC V3 ICC_SRE_ELx system interface.
This initialization can be done at 'EL3' only.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Swap this out and make the status a parameter.
Leave a couple of cases of DT_NODE_HAS_COMPAT().
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
These are redundantly checking a node's status twice.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Usually, we want to operate only on "available" device
nodes ("available" means "status is okay and a matching binding is
found"), but that's not true in all cases.
Sometimes we want to operate on special nodes without matching
bindings, such as those describing memory.
To handle the distinction, change various additional devicetree APIs
making it clear that they operate only on available device nodes,
adjusting gen_defines and devicetree.h implementation details
accordingly:
- emit macros for all existing nodes in gen_defines.py, regardless
of status or matching binding
- rename DT_NUM_INST to DT_NUM_INST_STATUS_OKAY
- rename DT_NODE_HAS_COMPAT to DT_NODE_HAS_COMPAT_STATUS_OKAY
- rename DT_INST_FOREACH to DT_INST_FOREACH_STATUS_OKAY
- rename DT_ANY_INST_ON_BUS to DT_ANY_INST_ON_BUS_STATUS_OKAY
- rewrite DT_HAS_NODE_STATUS_OKAY in terms of a new DT_NODE_HAS_STATUS
- resurrect DT_HAS_NODE in the form of DT_NODE_EXISTS
- remove DT_COMPAT_ON_BUS as a public API
- use the new default_prop_types edtlib parameter
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
This commit adds basic support for nRF52820 SoC.
Changes affect introducing:
- architecuture files (dtsi)
- configuration of nrfx drivers
- adaptation of inclusions based on chosen SoC
Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
Changes:
- Added all required board files in /boards/arm/96b_aerocore2
- Modified pinmux for stm32f4
Most of the changes in this PR is based on reverse-engineering of the
PCB layout and following commits in the PX4 firmware repository for
the same board. The manufacturer does not provide and or generate
schematics and pinout tables for this board.
This PR includes almost all of the interfaces connected to the STM32
MCU, the only thing not included is the J9 and J8 headers that connect
to a 96Boards baseboard.
These headers are not vital to the functionality of the Aerocore2.
Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
Add STM32F427. This is mainly aimed towards the stm32f427vi.
Changes:
- Add stm32f427 support based on previous work
done for the stm32f429.
- Rework currunt stm32f429 implimentation to now
be based on stm32f427.
- Introduce dedicated dtsi for the VI variant of both
stm32f427 and stm32f429. This is done to prevent stm32f4.dtsi
from being included twice.
Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
The SAM V71 SoC configuration currently selects the `ARM_MPU` symbol
and this effectively forces MPU usage on the SoC.
This commit removes `ARM_MPU` selection from the SoC Kconfig since it
is intended to be selected by a board, and the `CPU_HAS_ARM_MPU` symbol
already indicates that the SoC supports ARM MPU.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The SAM E70 SoC configuration currently selects the `ARM_MPU` symbol
and this effectively forces MPU usage on the SoC.
This commit removes `ARM_MPU` selection from the SoC Kconfig since it
is intended to be selected by a board, and the `CPU_HAS_ARM_MPU` symbol
already indicates that the SoC supports ARM MPU.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Add initial support for Broadcom Viper SoC.
It has ARM Cortex-M7 and Cortex-A72 cores.
Signed-off-by: Arjun Jyothi <arjun.jyothi@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Use MSI as PLL source. This enables to run system clock at 110MHz.
To achieve this, voltage regulator should be set to scale 0.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This patch defines the dma feature for the stm32wbXX
and the dmamux feature for the stm32wb55x
soc series from STMicroelectronics
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add support for ADC on H7 series. Note that ADC1 and ADC2 share the same
register set, so it is added as "adc1_2".
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
All pin configuration for ATMEL SAM SoC come from devicetree so we can
now remove the soc_pinmap.h header files.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert i2s_sam_ssc driver to utilize devicetree. We replace Kconfig
options for specifying the DMA configuration (channel, DMA device name)
with getting that from devicetree. We also get pincfg from devicetree,
however we still have Kconfig sybmols to specify if the RF or RK pin is
enabled.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Due to a typo compiling the WWDG on the g4 family does not
work. This adds the correct include filename.
Signed-off-by: Richard Osterloh <richard.osterloh@gmail.com>
High Speed Flexcomm device that handles high speed SPI transfer are
mapped to the same High Frequency clock that the ARM core uses.
This allows for higher frequency SPI traffic.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
Port the usage of the timeouts to the new timeout API, in order to be
able to deselect the legacy timeout option.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Convert to using DT_INST_LABEL() in the dma driver and convert dma users
to use the DMA property macros to get the dma controller name. We make
the assumption in the drivers that there is a single DMA controller
instance.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Some Kinetis SoCs have an instance of the the TPM module
that can be used for PWM control. As such, add the necessary
configurations to enable it on the SoCs that support it, as well as
enable the clock for the module to function.
In this case, the enablement is done only for the KW41Z SoCs,
but there are other SoCs that support it, f.i. KW38Z
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Enable I2S_STM32 in the soc common part, so it will no
longer be required in board default configuration.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Rename DT_HAS_NODE to DT_HAS_NODE_STATUS_OKAY so the semantics are
clear. As going forward DT_HAS_NODE will report if a NODE exists
regardless of its status.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert DT_CODE_PARTITION_{OFFSET,SIZE} to use new
DT_REG_ADDR/DT_REG_SIZE macros instead based on
DT_CHOSEN(zephyr_code_partition).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The riscv linker scripts utilize DT_FLASH_BASE_ADDRESS and
DT_FLASH_SIZE, as we want to phase out the old generator we need to
replace these defines with macros from devicetree.h.
We support two flash configurations at this point, either a QSPI flash
like on the hifive board or a SoC flash like on the rv32m1_vega. We
update the linker scripts to check the compat of the zephyr,flash node
and based on if its 'jedec,spi-nor' or 'soc-nv-flash' we determine how
to extract the "flash" base address and size.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
As we phase out per instance Kconfig symbols convert to utilize
DT_NODELABEL for SPI and I2C instances instead.
Also updated comments to change from FLEXCOMM8 to HSLSPI.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Remove DT_ADC_{0..2}_NAME from dts_fixup.h, if this casues the
dts_fixup.h file to be empty we remove the file as well.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Reworked sam_gmac driver to get pin ctrl/mux configuration information
from the device tree instead of via Kconfig and defines in soc_pinmap.h
We remove defines from soc_pinmap.h that are no longer needed due to
getting all that information from devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit adds the `devicetree.h` header inclusion in the Atmel SAM-
family SoC header files, as required by the ARM SoC conventions.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit adds the `devicetree.h` header inclusion in the Atmel SAM0-
family SoC header files, as required by the ARM SoC conventions.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Enable the driver for the Kinetis Digital-to-Analog (DAC) modules
present in the NXP Kinetis K6x SoC series.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Enable the driver for the Kinetis Digital-to-Analog (DAC32) module
present in the NXP Kinetis KE1xF SoC series.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Remove dts_fixup.h files that are needed anymore, remove defines that
are used, and replace defines with new DT macros.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move defines for _RAM_ADDR, _RAM_SIZE, _ROM_ADDR, and _ROM_ADDR into
the linker.ld and thus remove dts_fixup.h. We rework to use
DT_REG_ADDR and DT_REG_SIZE on DT_CHOSEN(zephyr_sram) and
DT_CHOSEN(zephyr_flash).
Also fixup use of _RAM_ADDR/_RAM_SIZE in newlib/libc-hooks.c.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Remove dts_fixup.h files that are not used (empty) or the defines aren't
used anymore and thus can be removed.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert linker scripts and arc_mpu_regions.c setup to use new
devicetree.h macros to extract the base address and size of the various
memory regions (DDR, SRAM, FLASH, DCCM, ICCM). We also remove the
scaling up and down since DT_REG_SIZE() returns the value in bytes.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Rework x86 linker scripts to use DT_REG_ADDR/DT_REG_SIZE on
DT_CHOSEN(zephyr_sram) and DT_CHOSEN(zephyr_flash). As part of this
we remove the dts_fixup.h. Using DT_REG_SIZE means we don't have to
adjust the sizes by 1024.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Remove dts_fixup.h files that are needed anymore, remove defines that
are used, and replace defines with new DT macros.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Replace DT_SNPS_ARCEM_0_CLOCK_FREQUENCY with a PATH based reference
to cpu@0 (DT_PATH(cpus, cpu_0)) and than getting the clock_frequency
property:
DT_SNPS_ARCEM_0_CLOCK_FREQUENCY ->
DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert from DT_MMIO_SRAM_10000000_BASE_ADDRESS to
DT_REG_ADDR(DT_NODELABEL(ddr0)) and similar for
DT_MMIO_SRAM_10000000_SIZE to DT_REG_SIZE().
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Complete STM32 conversion to new DT macros by removing
remaining occurences of DT_ST_STM32_ADC_FOO_LABEL.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
When we converted the GPIO driver to the new GPIO API we didn't update
the MMU mapping defines. Use the macros from devicetree.h and
nodelabel's to get the register base address and sizes for the GPIO
blocks.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Complete STM32 conversion to new DT macros by removing
remaining occurences of DT_ST_STM32_ADC_FOO_LABEL.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
During devicetree macro changes, LPSRAM_BOOT_VECTOR_ADDR
pointed to another macro which was renamed to a non-existent
one. Fix it so that SMP builds again.
Fixes#24720
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Rework the atom/linker.ld to match how ia32/linker.ld works with regards
to how PHYS_LOAD_ADDR & PHYS_RAM_ADDR are set based on CONFIG_XIP and
from which DT_PHYS_{RAM,LOAD}_ADDR defines. We update the minnowboard
dts and atom.dtsi files to keep in sync with this.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert ocram and sdram regions to use new macro DT_REG_ADDR() and
DT_REG_SIZE() with DT_NODELABEL to determine the various memories size
and base address.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use new DT_INST macros throughout. Removed per
instance Kconfig symbols and replaced with DT_NODELABEL references
where needed.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert the code for setting the clock IP source of the various IPs
present in the NXP KE1xF SoC series to the new DT API.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Convert driver to use the new device tree macro's instead of
dts_fixup.h based macros. This moves us closer to removing both
dts_fixup.h and per instance Kconfig symbols.
The pinmux_mchp_xec is also being updated since it's using DT
from GPIO.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Convert driver to use the new device tree macro's instead of
dts_fixup.h based macros. This moves us closer to removing both
dts_fixup.h and per instance Kconfig symbols.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Convert driver to use instance macro's instead of dts_fixup.h based
macros. This moves us closer to removing both dts_fixup.h and per
instance Kconfig symbols.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Replace DT_ARM_CORTEX_*_0_CLOCK_FREQUENCY with a PATH based reference
to cpu@0 (DT_PATH(cpus, cpu_0)) and than getting the clock_frequency
property:
DT_ARM_CORTEX_*_CLOCK_FREQUENCY ->
DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit renames the Kconfig `FLOAT` symbol to `FPU`, since this
symbol only indicates that the hardware Floating Point Unit (FPU) is
used and does not imply and/or indicate the general availability of
toolchain-level floating point support (i.e. this symbol is not
selected when building for an FPU-less platform that supports floating
point operations through the toolchain-provided software floating point
library).
Moreover, given that the symbol that indicates the availability of FPU
is named `CPU_HAS_FPU`, it only makes sense to use "FPU" in the name of
the symbol that enables the FPU.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Use DT_INST_FOREACH macro to combine code used for multiple instances.
Remove unnecessary Kconfig options and dts fixups for GPIO instances.
A side-effect to using DT_INST_FOREACH is that GPIO ports A0 and A3
are now enabled, whereas they were originally disabled by default as
an optimization.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
Rename DT_L2_SRAM_* to just L2_SRAM_* and set it using new DT macros.
Do something similar for DT_LP_SRAM_* renamed to LP_SRAM_*
Updated the intel_gna driver as it used the DT_L2_SRAM_* defines.
This change also lets us remove dts_fixup.h on intel_s1000 and
intel_apl_adsp SoCs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
