This adds a new config option for SAM0 targets that use the BOSSA
bootloader. If the CDC ACM driver is also enabled, then the
programmer can automatically reset the board into the bootloader for
programming.
Signed-off-by: Michael Hope <mlhx@google.com>
x19 is callee saved register. z_arch_el3_plat_init being a callee,
it should save it before using it. However, at this point, stack
has not been setup. So, let's just use x20 instead which is not
being used caller yet. This bug was causing VBAR_EL1 corruption,
but since [10:0] bits are reserved, bug was hidden.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
The `TEXT_SECTION_OFFSET` symbol is used to specify the offset between
the beginning of the ROM area and the address of the first ROM section.
This commit renames `TEXT_SECTION_OFFSET` to `ROM_START_OFFSET` because
the first ROM section is not always the `.text` section.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
In case of dualcore, STM32H7, STM32W and STM32MP1,
protect concurrent register write access with HSEM.
Done for following drivers:
clock_control, counter, flash, gpio, interrupt_controller
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
When building for nRF5340 PDK board, enable Kconfig option
for Erratum 19. Do not enable when building on nRF5340 DK.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add and mark PCIe highmem outbound memory as nGnRnE device memory
in Viper SoC MMU configuration.
Increase VA/PA bits to 36-bits to support the same.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
This patch introduces the support of low power modes
for the STM32WBxx from STMicroelectronics based on the lptim
Here, the power modes are sleep modes have lptimer as wakeup source.
The sleep modes are configured by the SYS_POWER_MANAGEMENT.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add initial support for nuvoton numicro m48x SoC series, basic
init and uart functionality are covered with gpio and clock
directly relies on HAL.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
This enables PWM and connects it to the main LED. Tested by running
samples/basic/blinky_pwm and /fade_led.
Signed-off-by: Michael Hope <mlhx@google.com>
The SAM0 Timer/Counter for Control Applications can act as a counter
or generator. Add a binding for the TCC in PWM mode and helper to
check the compat mode.
Signed-off-by: Michael Hope <mlhx@google.com>
Add reset interrupt handlers for all three types of reset
interrupts that iProc PCIe EP can receive - namely PERST,
INB PERST and FLR.
Signed-off-by: Shivaraj Shetty <shivaraj.shetty@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Change the SAM0 to match other boards by selecting the SAM0 specific
driver when a driver class is selected.
For example, automatically enable CONFIG_SPI_SAM0 when CONFIG_SPI is
enabled.
Signed-off-by: Michael Hope <mlhx@google.com>
Only boards with at least 64K Flash will activate MPU because:
MPU + UERSPACE + All switches implicity activated
(CONFIG_MPU_STACK_GUARD, CONFIG_ARM_STACK_PROTECTION ...)
will consume about 40K Flash
(value computed on nucleo_f767_zi on tests/arch/arm/arm_ramfunc/).
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
The PWM drivers has been refactored using the HAL LL API. Not only that,
but the set pin_set function is now faster, as channel output compare is
just initialized if needed.
NOTE: Has been tested using H743zi board for now.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Those MCUs have 2KB RAM and 16KB FLASH memory, but they are still
powerful enough to run small configuration of Zephyr RTOS.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Added / Tested support for RNG on the STM32F767ZI nucleo board.
Updated the SoC defconfig to auto-enable the driver when
ENTROPY_GENERATOR is enabled, and updated the board README.
Signed-off-by: Bilal Wasim <bilalwasim676@gmail.com>
This patch introduces the support of low power modes
for the STM32L4xx from STMicroelectronics based on the lptim
Here, the power modes are sleep modes with lptimer as wakeup.
Depending on the SYS_POWER_MANAGEMENT configuration.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
tested on mimxrt1060_evt
MEMORY_NOCACHE is needed
test on frdmk64f
special test slot need configure with
CONFIG_DMA_TEST_SLOT_START
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
This option controls whether additional BLE support is
enabled for the cc13xx_cc26xx platform in hal/ti and
subsys/bluetooth.
Signed-off-by: Christopher Friedt <chrisfriedt@gmail.com>
Introduce switch to allow board configuration for VCI pins to
remain HW-controled depending on the design.
Currently pins are always configured as GPIOs which is not always
desirable.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
The NXP's Kinetics K66F is able to run with max frequency of 180MHz.
To achieve this goal the SMC's PMPROT and PMCTRL registers need to be
adjusted.
On the contrary the K64F doesn't support HSRUN run mode.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This option enables support for High Speed RUN operation mode for
K66F. The K64F SoC doesn't support this mode.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Add the necessary clock configuration to support STM32L-based
SoCs. This change likely adds support for other STM32 SoCs as well
since the HSI48 clock is configured for all SoCs that support it
(except the STM32L4x) instead of just the STM32G4X.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
This commit fixes Cortex-M header inclusions from the deprecated paths.
The Cortex-M headers were relocated from `include/arch/arm/cortex_m` to
`include/arch/arm/aarch32/cortex_m` by the refactoring done in the
commit d048faacf2.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This is defining the SYS_CLOCK_TICKS_PER_SEC default value
depending on the LPTIM CLOCK frequency in case of LPTIMER,
to get a TICK value as a divider of the LPTIM clock source.
It gives a better result in formulas when converting
ticks to count unit.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Several reviewers agreed that DT_HAS_NODE_STATUS_OKAY(...) was an
undesirable API for the following reasons:
- it's inconsistent with the rest of the DT_NODE_HAS_FOO names
- DT_NODE_HAS_FOO_BAR_BAZ(node) was agreed upon as a shorthand
for macros which are equivalent to
DT_NODE_HAS_FOO(node) && DT_NODE_HAS_BAR(node) &&
- DT_NODE_HAS_BAZ(node), and DT_HAS_NODE_STATUS_OKAY is an odd duck
- DT_NODE_HAS_STATUS(..., okay) was viewed as more readable anyway
- it is seen as a somewhat aesthetically challenged name
Replace all users with DT_NODE_HAS_STATUS(..., okay), which is
semantically equivalent.
This is mostly done with sed, but a few remaining cases were done by
hand, along with whitespace, docs, and comment changes. These special
cases include the Nordic SOC static assert files.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The Atmel SAM D21 SoC, according to the original Atmel datasheet
(Atmel-42181N), has 28 interrupt lines (0-27).
There have been mysterious changes in the number of interrupt lines and
on-chip peripherals in the recent Microchip datasheet releases, but
there is no explicit information available for this (e.g. PCN), so we
take the safest approach by assuming the lowest interrupt line number.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
PSA level 1 requires secure boot. TF-M BL2 is the official
secure boot loader. It needs a BL2_HEADER_SIZE offset.
Align nonsecure address with TF-M's NS slot while TF-M BL2 enabled.
Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
Add infineon XMC4 series UART support. Driver supports
only poll mode using XMCLib.
Out of 4 available UART's on SoC, only UART1 is confgired
by default in UART mode until GPIO & pinctrl support.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Add infineon xmc series with XMC4500 support. XMC series comes with,
- CPU operates upto 120MHz
- 3 RAM (PSRAM1 - code, DSRAM1 - data and DSRAM2 - communiation)
- upto 1MB flash
init: clock control & gpio is not done, so SoC initialization directly
relies on HAL. Core operating clock is stored in no_init section, which
is kept under DSRAM1. Only DSRAM1 is used until clock support. Using
PSRAM1 and DSRAM1 needs adaptation in linker script - planned for next
revision.
Note: SystemInit cannot be consumed directly due to vector table +
HAL linker dependency.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Add initilizations for:
- Cortex-A72 L2 Controller configurations. This initialization to
be done when cluster is in quiscent state.
- 'ICC_SRE_EL3' init to allow GIC V3 ICC_SRE_ELx system interface.
This initialization can be done at 'EL3' only.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Swap this out and make the status a parameter.
Leave a couple of cases of DT_NODE_HAS_COMPAT().
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
These are redundantly checking a node's status twice.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
