Add initial support for Decawave DW1000
IEEE 802.15.4-2011 UWB transceiver.
Driver has basic functionality. Additional functions such
as reading out timestamps and delayed TX were implemented
for test purposes, but also require support in the 802154
subsystem.
Register, sub-register, and defaults defines in the file
ieee802154_dw1000_regs.h are taken from the Decawave's
DW1000 driver for the Mynewt OS.
Signed-off-by: Johann Fischer <j.fischer@phytec.de>
Binding used for LPC random number generator hardware.
Describes RNG device node in LPC5xxx SoCs device tree peripherals.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
Add support for ADC on H7 series. Note that ADC1 and ADC2 share the same
register set, so it is added as "adc1_2".
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Convert i2s_sam_ssc driver to utilize devicetree. We replace Kconfig
options for specifying the DMA configuration (channel, DMA device name)
with getting that from devicetree. We also get pincfg from devicetree,
however we still have Kconfig sybmols to specify if the RF or RK pin is
enabled.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert sam_xdmac driver to utilize devicetree. As part of the
controller binding we specify that dmas should contain a channel and the
perid for the DMA transaction.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The DS3231 is an I2C real-time clock with internal temperature
compensated oscillator, maintaining civil time to 1 s precision with
nominal 2 ppm accuracy from 0-40 Cel.
The basic functionality is exposed as a counter that is always running
at 1 Hz. Much more functionality is exposed as driver-specific API,
including the ability to translate between the time scale of the DS3231
and the time scale of the Zephyr uptime clock. This allows correlation
of events in the system clock to UTC, TAI, or whatever time scale is
used to maintain the DS3231.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Add a driver that can handle several instances of AT45 family chips,
which are enabled by specifying DT nodes for them with the "compatible"
property set to "atmel,at45" and other required properties like JEDEC
ID, chip capacity, block and page size etc. configured accordingly.
The driver is only capable of using "power of 2" binary page sizes in
those chips and at initialization configures them to work in that mode
(unless it is already done).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This header is physically related to the Adafruit Feather, but uses a
different pin numbering and exposes a slightly different set of pins.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Once the TPM driver and the required configs have been added,
now this patch enables the usage of the PWM framework on KW41Z
SoCs. As such, the DTS gets the proper nodes and the pinmuxing
is done according to the configuration requested.
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
The TPM (Timer/PWM Module) is a 2- to 8-channel timer which supports
input capture, output compare, and the generation of PWM signals to
control electric motor and power management applications.
This patch adds the driver and the binding necessary for instantiating
the driver. The work is based on the RV32M1 driver for TPM done by
Henrik Brix Andersen. A later patch will enable this driver to be used
for the KW41Z SoC, if PWM support is requested.
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
* Define USB driver for base stm32wb device.
* Enable USB for the nucleo_wb55rg board.
* Properly initialize USB power + clock for the platform.
Signed-off-by: Pete Johanson <peter@peterjohanson.com>
This patch introduces the periph to/from memory dma transfer
using the dmamux feature and define new values
for dma cells on client side
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Reworked sam_gmac driver to get pin ctrl/mux configuration information
from the device tree instead of via Kconfig and defines in soc_pinmap.h
We remove defines from soc_pinmap.h that are no longer needed due to
getting all that information from devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The Atmel SAM D5x and E5x series SoCs include the ARM memory protection
unit that supports up to 8 memory regions.
This commit adds the missing device tree MPU node to `samd5x.dtsi`,
which is used by both the SAM D5x and E5x series SoCs.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This patch is defining the DMA1 & 2 for the sm32l4 series
with 7 channels and support of mem2mem transfers
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This includes the dma cells as client for the spi
An example of the client part is defined in the dma.yaml
Consequently, bindings for the dmas property becomes then 'not required'
Including dma.yaml is not needed as dma properties
are now part of base.yaml
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add device tree nodes for the Digital-to-Analog (DAC) modules present
in the NXP Kinetis K6x series.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Add device tree node for the Digital-to-Analog (DAC32) module present
in the NXP Kinetis KE1xF series.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Add initial devicetree for the NXP LPC55S16. Only non-secure (ns)
access is supported for now.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Do not assume in the SoC level device trees that NXP Kinetis FlexTimer
nodes will always be configured as PWM. Instead, configure FlexTimer
nodes for PWM at the board level for NXP Kinetis boards.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Rework the atom/linker.ld to match how ia32/linker.ld works with regards
to how PHYS_LOAD_ADDR & PHYS_RAM_ADDR are set based on CONFIG_XIP and
from which DT_PHYS_{RAM,LOAD}_ADDR defines. We update the minnowboard
dts and atom.dtsi files to keep in sync with this.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Rework the devicetree to utilize new DT_INST macros and extract per
instance data for clocks from devicetree.
We add a property ('calib-offset') for the SAM{D,E}5x family of SoCs
that is the bit position offset from ADC0 BIASCOMP in the NVM Software
Calibration Area Mapping. For ADC0 this is typically 0 and for ADC1
this will be 14.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In STM32 can driver CAN2 instance need to know the base address
of CAN1 instance which is referenced as master can.
Add this information as an optional property to stm32 can binding.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
By defaut, only one uart is used as console.
Disable unused peripherals in dts to avoid
conflicts (issue #23475), save memory footprint,
and reduce the boot time.
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Convert driver to use the new device tree macro's instead of
dts_fixup.h based macros. This moves us closer to removing both
dts_fixup.h and per instance Kconfig symbols.
The pinmux_mchp_xec is also being updated since it's using DT
from GPIO.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Convert driver to use the new device tree macro's instead of
dts_fixup.h based macros. This moves us closer to removing both
dts_fixup.h and per instance Kconfig symbols.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add local-mac-address on DT and enable it on rf2xx driver. If user
define local-mac-address this value will be used as default mac address.
Otherwise driver automatically add a random mac address.
On application level user can change default mac address using net_mgmt
command with NET_REQUEST_IEEE802154_SET_EXT_ADDR parameter defined on
include/net/ieee802154_mgmt.h header.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Replace DT_FLASH_DEV_NAME with DT_CHOSEN_ZEPHYR_FLASH_CONTROLLER_LABEL.
We now set zephyr,flash-controller in the chosen node of the device
tree to the flash controller device.
NOTE: For a SoCs with on die flash, this points to the controller and
not the 'soc-nv-flash' node. Typically the controller is the
parent of the 'soc-nv-flash' node).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Rework the devicetree to utilize new DT_INST macros and extract per
instance data for clocks from devicetree. Move the prescaler setting
from Kconfig to devicetree as well.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add clock references for ADC and TC devices. Update the bindings for
these devices to require clocks property and update the dtsi files to
have the clock info.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Rework the devicetree to utilize new DT_INST macros and extract per
instance data for clocks and dma from devicetree. We update the
atmel,sam0-spi binding for dma to replace the rxdma and txdma
properties with proper 'dmas' property.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Rework the devicetree to utilize new DT_INST macros and extract per
instance data for clocks and dma from devicetree. We update the
atmel,sam0-i2c binding for dma to replace the dma property with
proper 'dmas' property.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add pinctl support for the SAM SPI device. We update the SPI
binding to have pinctrl-0 bindings that are expected to have
at least phandles for MISO, MOSI, and SPCK, but might also have
various chip selects as well.
The pinctrl nodes will have an 'atmel,pins' property that describes the
GPIO port, pin and periphal configuration for that pin.
We update sam*-pinctrl.dtsi files with all the various pin ctrl
configuration operations supported by the given SoC family. These
files are based on data extracted from the Atmel ASF HAL
(in include/sam<FAMILY>/pio/*.h).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add wdt0 node labels for all watchdogs. Keep the existing wdt node
labels in place for backwards compatibility.
Add a wdt1 node to the nRF5340 application core .dtsi, but leave it
disabled. Leave the wdt node's label set to "WDT" on this core for
backwards compatibility also, in case any users are getting it with a
string literal instead of asking the devicetree. This can be changed
later after this round of watchdog changes has been shaken out and
tested more.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The SAM D5x and E5x series SoCs include the "Cortex-M4F" core, not the
FPU-less "Cortex-M4" core.
This commit fixes the incorrect CPU compatible for the SAM D5x and E5x
SoCs (note that this file is included by `same5x.dtsi`, which is used
as the base device tree header for the SAM E5x series).
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Adding port information for uart tx and rx pins in dts, so that it can
be more systematically retrieved in the uart driver.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
Convert driver to use DT_INST_ defines. As part of this conversion we
remove the Kconfig options for per GPIO controller enables and instead
get that information from device tree. This means we now disable each
GPIO controller by default in the DTS and have each board dts enable the
GPIO controller ports it needs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Reworked adc_sam_afec driver to utilize new DT_INST macros as part of
this rework we also now get pin ctrl/mux configuration information
from the device tree instead of via Kconfig and defines in soc_pinmap.h
We remove defines from dts_fixup.h and soc_pinmap.h and associated
Kconfig symbols that are no longer needed due to getting all that
information from devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Rework the devicetree to utilize new DT_INST macros and extract per
instance data for clocks and dma from devicetree. We update the
atmel,sam0-uart binding for dma to replace the rxdma and txdma
properties with proper 'dmas' property.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move the atmel,sam0-dmac binding under the dma binding dir and add
cell information for channel and trigger source. Update the associated
dtsi files to match these changes.
This is in prep of ATMEL SAM0 SERCOMM devices like UART, I2C, and SPI to
user proper 'dmas' property to specify the dma info to use.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add support for the GCLK, MCLK, and PM clock controllers. Add bindings
and devicetree nodes associated with these clock controllers. Also add
clock references for the SERCOM peripheral set to allow those drivers
(i2c, spi, uart) to utilize this information.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit renames `samd.dtsi` to `samd2x.dtsi` since this DTS header
is specific to the SAM D2x series and its derivatives (e.g. SAM R21).
Note that the SAM D5x series uses a different DTS header file (i.e.
`samd5x.dtsi`) due to the vast differences, and the future SAM D1x will
have to use a separate DTS header to be sensible anyway.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
There was a typo bug in the SRAM ranges property that causes the SRAM
nodes to appear at the wrong addresses.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add pinctl support for the SAM TWI and TWIHS I2C devices. We update
the TWI and TWIHS I2C bindings to have pinctrl-0 bindings that are
expected to have 2 phandles to the TWCK & TWD pinctrl nodes.
The pinctrl nodes will have an 'atmel,pins' property that describes the
GPIO port, pin and periphal configuration for that pin.
We update sam*-pinctrl.dtsi files with all the various pin ctrl
configuration operations supported by the given SoC family. These
files are based on data extracted from the Atmel ASF HAL
(in include/sam<FAMILY>/pio/*.h).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
We've had clocks in base.yaml but didn't have clock-names. Add it to
base.yaml with similar functionality to interrupt-names, reg-names, etc.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use new DT_INST macros throughout. We remove the
aliases and use nodelabel instead in the soc_gpio.h to determine the
label for the specific gpio controller.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
enable the interrupt functionality for sx1509b gpio expander,
when the CONFIG_GPIO_SX1509B_INTERRUPT config is enabled.
The gpio pin used for interrupt should be configured in the
device tree sx1509b node before enabling the interrupt
configuration.
Signed-off-by: Viraaj Somayajula <sviraaj@zedblox.com>
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Mark all the individual PWMs as disabled in dts and enable the one
explicitly used on the mimxrt1064_evk.dts in the board dts file.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Have nodelabels match the SoC docs so when a nodelabel reference is
made in the code its easier to relate to the SoC.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
DAC (digital to analog converter) peripheral driver with a generic API
suitable for most MCUs (only basic DAC features considered).
Signed-off-by: Martin Jäger <martin@libre.solar>
Add pinctl support for the SAM UART and SAM USART devices. We update
the UART and USART bindings to have pinctrl-0 bindings that are expected
to have 2 phandles to the RX & TX pinctrl nodes.
The pinctrl nodes will have an 'atmel,pins' property that describes the
GPIO port, pin and periphal configuration for that pin.
We add sam*-pinctrl.dtsi files with all the various pin ctrl
configuration operations supported by the given SoC family. These
files are based on data extracted from the Atmel ASF HAL
(in include/sam<FAMILY>/pio/*.h).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The atmel,pins property will be utilized to describe pin mux
configuration. The property will be a phandle-array in which the
phandle points to the given GPIO port the pin is on, the pin number, and
the mux configuration.
This change updates the atmel,sam-gpio binding to support that
phandle-array and updates the associated SoC dtsi files as well.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add dts support for the headers on Adafruit Feather boards.
This will allow adding FeatherWing boards as shields.
Signed-off-by: Richard Osterloh <richard.osterloh@gmail.com>
Move the majority of the device tree into nxp_lpc55S6x_common.dtsi and
use ranges to handle the different address may for non-secure.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Have nodelabels match the SoC docs so when a nodelabel reference is
made in the code its easier to relate to the SoC.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Have nodelabels match the SoC docs so when a nodelabel reference is
made in the code its easier to relate to the SoC.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Have nodelabels match the SoC docs so when a nodelabel reference is
made in the code its easier to relate to the SoC.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Have nodelabels match the SoC docs so when a nodelabel reference is
made in the code its easier to relate to the SoC.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Have nodelabels match the SoC docs so when a nodelabel reference is
made in the code its easier to relate to the SoC.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Have nodelabels match the SoC docs so when a nodelabel reference is
made in the code its easier to relate to the SoC.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Have nodelabels match the SoC docs so when a nodelabel reference is
made in the code its easier to relate to the SoC.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit adds a GMAC instance to the SAM E5x device tree, along with
the refactoring necessary to specify the SAM E5x-specific components.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The SAM4E GMAC version can use only MII as phy-connection-type. This
update the current default RMII value to MII.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This add the following options to GMAC device tree bindings:
- max-frame-size
- max-speed
- phy-connection-type
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This commit adds a GMAC instance to the SAM 4E device tree.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This commit fixes the incorrect memory (FLASH and SRAM) size
specification in the device tree and the board test yaml files.
The `qemu_cortex_r5` board (using `fdt-single_arch-zcu102-arm.dtb` FDT)
has 64MiB RAM at the address 0 and 32MiB QSPI flash at 0xc0000000.
QEMU `info mtree`:
0000000000000000-ffffffffffffffff (prio 0, i/o): memory@00000000
0000000000000000-000000000002ffff (prio 0, ram): ddr_bank1_1@0x0
0000000000030000-000000000003ffff (prio 0, ram): ddr_bank1_2@0x30000
0000000000040000-0000000003ffffff (prio 0, ram): ddr_bank1_3@0x40000
00000000c0000000-00000000c1ffffff (prio 0, i/o): lqspi
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Now that all entropy drivers use DTS we can remove HAS_DTS_ENTROPY being
set everywhere as well as Kconfig ENTROPY_NAME since that is now coming
from DT_ENTROPY_NAME.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Replace CONFIG_ENTROPY_NAME with DT_CHOSEN_ZEPHYR_ENTROPY_LABEL. We now
set zephyr,entropy in the chosen node of the device tree to the entropy
device.
This allows us to remove CONFIG_ENTROPY_NAME from dts_fixup.h. Also
remove any other stale ENTROPY related defines in dts_fixup.h files.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
dmas and dma-names properties could be used by a wide range
of potential dma client, hence put them in base.yaml, as
optional properties.
Since current stm32-i2s driver implementation only support
dma, set these properties as required.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add a property to the openisa,rv32m1-gpio binding that relates the GPIO
node to the pinmux PORT node.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use DT_INST macros and remove related board per
instance Kconfig symbol usage.
Updated the openisa,rv32m1_vega-pinmux binding to require the label
property and updated the rv32m1.dtsi to add label properties for the
pinmux nodes.
Also update gpio_basic_api test to use DT_NODELABEL.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
As prep for drivers being converted to utilize DT_INST and removal of
per instance Kconfig symbols, move soc.c code to utilize DT_NODELABEL
instead.
Also rename various node labels to match the SoC docs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Don't assume in the soc level device trees that flexcomm nodes will
always be configured as spi. Instead, configure flexcomm nodes at the
board level for lpcxpresso55s69 and lpcxpresso54114 boards.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Don't assume in the soc level device trees that flexcomm nodes will
always be configured as usart. Instead, configure flexcomm nodes at the
board level for lpcxpresso55s69 and lpcxpresso54114 boards.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Don't assume in the soc level device trees that flexcomm nodes will
always be configured as i2c. Instead, configure flexcomm nodes at the
board level for lpcxpresso55s69 and lpcxpresso54114 boards.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The flexcomm peripheral on lpc socs can be configured into uart, spi,
i2c, or i2s mode. Introduce a shared device tree binding that gets
included by the more specific driver type bindings.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The st,stm32l0-flash-controller did not have a binding, add one for it.
Also made a comment in stm32l0.dtsi that the driver doesn't currently
support this controller.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The flash at 0 is a cfi-flash and its 2 banks each that are 64M.
Update qemu-virt-a53.dtsi to reflect the proper flash config, however we
comment out the second bank of flash for now because zephyr,flash can
only handle one value in the reg property.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Group all the GPIO controllers under a pinctl node so that we have a
container for pinmux configuration data.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Adds i2c device tree bindings and nodes for the lpc54xxx and lpc55s6x
socs in preparation for adding a new i2c driver.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Make sure every flash controller has a node label "flash_controller".
This will make it easier to refer to the SoC NVMC node when necessary.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
With the introduction of the new device-tree macros it is now possible
to use the settings for speed and flow-control from the bus node instead
of having the same properties on the esp node itself.
Signed-off-by: Tobias Svehagen <tobias.svehagen@gmail.com>
Define rng nodes for all SoCs featuring the RNG peripheral,
so that the entropy_nrf5 driver can be converted to DTS.
For the network core in nRF5340, align the RNG interrupt priority with
what is used as the default value in (almost) all other DTS nodes.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Make the label property required for "arm,cmsdk-gpio" compatible
nodes. Update binding to mark the 'label' property required and updated
associated .dts files to add a 'label' property if it didn't exist.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Currently supported nRF SoCs featuring the second GPIO port (P1) do not
have all 32 pins implemented in that port. Add the "ngpios" property
in gpio1 nodes for these SoCs, so that they don't take the default
value of 32 to indicate the number of available pins but use instead:
- 10 for nRF52833
- 16 for nRF52840
- 16 for nRF5340 (both application and network core)
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for the STM32L422Xb SoC. Base stm32l422.dtsi on
stm32l412.dtsi to be able to add the crypto device later.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Add a YAML, DTS node and driver support to utilize data from devicetree
for register address and driver name.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
64 kB of memory is reserved for the inter-processor
communication. this makes sense only if RPMsg is used.
Allow to use this memory for firmware data by default.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
And implement DT_ANY_INST_ON_BUS() in terms of it.
This makes some error messages quite a bit shorter by avoiding
UTIL_LISTIFY(), which has a nasty temper and tends to explode if not
treated gently.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
This commit adds a GMAC instance to the SAM V71 device tree, with the
chip revision-specific hardware queue count.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit adds a GMAC instance to the SAM E70 device tree, with the
chip revision-specific hardware queue count.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The label property of the fixed-partitions child binding was duplicated
with two different values. This is invalid yaml, but went unnoticed by
pyYAML. Removed first entry to preserve value produced by pyYAML
behavior of overwriting duplicates.
Signed-off-by: Trond Einar Snekvik <Trond.Einar.Snekvik@nordicsemi.no>
Added properties to support the core interrupt controller on the NIOS2
cpu cores and enable that support for the NS16550 UART.
We rename some compatibles so that the cpu core compatibles is unique.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add device tree binding for the NXP Kinetis Low Power Timer (LPTMR)
module. This module can either act as a 16 bit counter or a 16 bit
pulse counter.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
SIM core system clock is being used, but more importantly this will
enable to get the SIM clock controller in use for power management
purposes in MCUX ethernet driver.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Added device tree nodes and associated headers for
defined uarts on the stm32g0 and stm32g07x 8x parts.
Tested with uart on stm32g071rb disco board with usart3 going to stlink.
Using shell.
Signed-off-by: Kieran Levin <ktl@frame.work>
Use zero-padded 32-bit hex constants for the start address and
length so the fields are easier to compare. Correct the span of
the priority/claim region.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
