Add support for the polarity flag in the STM32 PWM driver.
STM32 boards using PWM have been updated accordingly.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Aliases defined for peripheral nodes in the nRF SoC definitions were
used in drivers to properly match the hardware instances.
After the drivers were converted to use the new DT API, these aliases
became needless.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Previously, DTS specification of physical RAM bounds did not
correspond to the actual bounds of system RAM as the first
megabyte was being skipped.
There were reasons for this - the first 1MB on PC-like systems
is a no-man's-land of reserved memory regions, but we need DTS
to accurately capture physical memory bounds.
Instead, we introduce a config option which can apply an offset
to the beginning of physical memory, and apply this to the "RAM"
region defined in the linker scripts.
This also fixes a problem where an extra megabyte was being
added to the size of system RAM.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Appropriate WS can be loaded automatically if
the display controller has integrated temperature
sensor or an external sensor is connected.
Signed-off-by: Johann Fischer <j.fischer@phytec.de>
Enable GPIO as a workaround to enable some SPI slaves are not correctly
controlled using the Flexcomm SPI device.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
Those MCUs have 2KB RAM and 16KB FLASH memory, but they are still
powerful enough to run small configuration of Zephyr RTOS.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
- Change default CPU Clock to 240MHz
(PLL is activated)
- I2C, UART will use sysclk from clock driver
- esp32_enable_peripheral replaced by
clock_control_on
Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
- Support PLL for Higher Frequencies 80,160,240 MHz
- Support XTAL Frequencies 26MHz, 40MHz
- Clock Driver can't be disabled, because all of the other drivers
will depend on it to get their operating Frequency based on chosen
clock source (XTAL/PLL).
- Add needed references to BBPLL i2c bus ROM functions.
- Add `rtc` node to Device Tree.
- Since All Peripherals Frequency is depending on CPU_CLK Source,
`clock-source` property added to CPU node
Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
Cleaned up flow control configuration. Added support for using only
cts or only rts.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
The STM32L072 and STM32L073 comes with a hardware random number
generator. Add this to the device tree.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
This allows referencing the CPU in the board-specific DTS file.
Also fix warnings by making the addresses lower case.
Signed-off-by: Michael Hope <mlhx@google.com>
Adds a new LPTIM binding for stm32 soc,
based on the timer binding. This will makes a specific filter
on dt_compat_enabled("stm32,lptim")
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add test cases that verify various bits and pieces of the legacy
devicetree macros match the new APIs.
Writing these test cases without giving rise to deprecated macro
warnings which might break people's CI if they build with -Werror
requires turning off the __WARN() generation in
devicetree_legacy_unfixed.h. The entire file is deprecated at this
point and must be explicitly enabled with an opt-in Kconfig option, so
there isn't any harm in doing this.
Nevertheless, take a minimally invasive approach to avoiding __WARN()
generation in gen_legacy_defines.py, to avoid the possibility of
breakage. This code is basically frozen anyway, so hacks like this
won't cause maintainability problems since it isn't being actively
maintained.
Use the new tests as fodder for a migration guide from the old API in
the documentation.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Remove some deprecated or obsolete functionality:
- the 'title:' key is now deprecated
- more than 2 levels of child-binding are now supported
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
At some point, "child-binding:" apparently only worked up to 2 levels
deep. That's not the case anymore, but add a regression test to make
sure that doesn't break. 3 levels deep ought to be enough for anyone.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The interrupts generated by the generic timer behave in
a level-sensitive manner. Change the DT to reflect the same.
Fixes: #25585
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Add the missing node and bindings. This is a secure-mapped peripheral,
so do not add it to the common include file
nrf5340_cpuapp_common.dtsi.
Fixes: #25493
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
In aarch64 DTs, priority and flags cells have been swapped,
fix the same.
Correct interrupt property per the GIC binding document
looks like:
interrupts = <irq_type irq_num irq_flags irq_priority>;
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Adds the required #io-channel-cells property to kinetis k8x and kv5x
socs. We are now consistently defining this property for all
nxp,kinetis-adc16 compatible nodes.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Allow configuring the clock prescaler divider for the NXP Kinetis
FlexTimer. Setting the prescaler to a lower value allows for much
higher resolution/accuracy for the generated PWM waveforms.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The macro iterates through the list of child nodes in a DT_DRV_COMPAT
instance and invokes provided macro for each node.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Instead of having a Kconfig property, if there is no local-mac-address
property in the devicetree than we'll generate a unique MAC address
based on unique ID registers on the SoC.
We remove the local-mac-address properties in the SoC dtsi files to
match the default behavior that existed before (ie, unique MAC address)
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add definition of zephyr,random-mac-address property that conveys to a
driver to utilize a random MAC address if the driver supports this
feature.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add infineon XMC4 series UART support. Driver supports
only poll mode using XMCLib.
Out of 4 available UART's on SoC, only UART1 is confgired
by default in UART mode until GPIO & pinctrl support.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Add infineon xmc series with XMC4500 support. XMC series comes with,
- CPU operates upto 120MHz
- 3 RAM (PSRAM1 - code, DSRAM1 - data and DSRAM2 - communiation)
- upto 1MB flash
init: clock control & gpio is not done, so SoC initialization directly
relies on HAL. Core operating clock is stored in no_init section, which
is kept under DSRAM1. Only DSRAM1 is used until clock support. Using
PSRAM1 and DSRAM1 needs adaptation in linker script - planned for next
revision.
Note: SystemInit cannot be consumed directly due to vector table +
HAL linker dependency.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
For HPET devices, configure it with fixed delivery mode because HPET
timer interrupt is needed to fuel the scheduler for all CPUS.
For all other type of devices, like UART, I2C, GPIO, Ethernet, etc.
configure them as lowest priority delivery mode, in which IO APIC
delivers the interrupt to the processor core that is executing at the
lowest priority among all the processors listed in the specified
destination. In this case, the device drivers can avoid the trouble of
handling repeated interrupts delivered to all CPUS.
Signed-off-by: Zide Chen <zide.chen@intel.com>
The label property does not need to have its type set
explicitly to string, so remove it.
Signed-off-by: Anthony Brandon <anthony@amarulasolutions.com>
By this commit USB audio class implementation is introduced
to Zephyr.
The Zephyr USB audio device class follows bellow
documentations:
- Universal Serial Bus specification rev2.0 (usb20.pdf)
- Universal Serial Bus Device Class Definition for Audio Devices
(audio10.pdf)
- Universal Serial Bus Device Class Definition for Audio Data Formats
(frmts10.pdf)
- Universal Serial Bus Device Class Definition for Terminal Types
(termt10.pdf)
Signed-off-by: Emil Obalski <emil.obalski@nordicsemi.no>
This commit adds support for nRF52820 development on nRF52833DK.
Changes afffects:
- Introduce files related to board description.
- Add blank documentation file (for future update).
- configuration files for build process.
Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
This commit adds basic support for nRF52820 SoC.
Changes affect introducing:
- architecuture files (dtsi)
- configuration of nrfx drivers
- adaptation of inclusions based on chosen SoC
Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
Add STM32F427. This is mainly aimed towards the stm32f427vi.
Changes:
- Add stm32f427 support based on previous work
done for the stm32f429.
- Rework currunt stm32f429 implimentation to now
be based on stm32f427.
- Introduce dedicated dtsi for the VI variant of both
stm32f427 and stm32f429. This is done to prevent stm32f4.dtsi
from being included twice.
Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
Update dtsi and pinmux macros for stm32f7 family. Add sdmmc1 to dts file
for stm32f746g_disco. Also add board specific configuration file for
fat_fs sample.
Signed-off-by: Helge Juul <helge@fastmail.com>
Update the dtsi for stm32l471 (which the higher SoCs are based on) to
support the stm32-sdmmc disk access device. Enable the device for the
stm32l496g_disco board, and update the pinmuxing.
Note that the stm32l496g_disco board also has a card detect gpio
(MFX_GPIO8), but this is not supported yet. When not specified the
driver will assume a card is present.
Signed-off-by: Anthony Brandon <anthony@amarulasolutions.com>
Add a disk access driver for the stm32 sdmmc component. The driver is
based around the stm32 cube HAL and uses the blocking API.
Signed-off-by: Anthony Brandon <anthony@amarulasolutions.com>
Add initial support for Broadcom Viper SoC.
It has ARM Cortex-M7 and Cortex-A72 cores.
Signed-off-by: Arjun Jyothi <arjun.jyothi@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
