drivers: i2c: i2c_sam0: rework devicetree support
Rework the devicetree to utilize new DT_INST macros and extract per instance data for clocks and dma from devicetree. We update the atmel,sam0-i2c binding for dma to replace the dma property with proper 'dmas' property. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala
Kumar Gala
parent
dbeb3ba32e
commit
b8ade7856d
2 changed files with 56 additions and 100 deletions
|
|
@ -6,7 +6,6 @@
|
|||
|
||||
#define DT_DRV_COMPAT atmel_sam0_i2c
|
||||
|
||||
|
||||
#include <errno.h>
|
||||
#include <device.h>
|
||||
#include <init.h>
|
||||
|
|
@ -733,48 +732,21 @@ static const struct i2c_driver_api i2c_sam0_driver_api = {
|
|||
};
|
||||
|
||||
#ifdef CONFIG_I2C_SAM0_DMA_DRIVEN
|
||||
#ifndef DT_ATMEL_SAM0_I2C_SERCOM_0_DMA
|
||||
#define DT_ATMEL_SAM0_I2C_SERCOM_0_DMA 0xFF
|
||||
#endif
|
||||
#ifndef DT_ATMEL_SAM0_I2C_SERCOM_1_DMA
|
||||
#define DT_ATMEL_SAM0_I2C_SERCOM_1_DMA 0xFF
|
||||
#endif
|
||||
#ifndef DT_ATMEL_SAM0_I2C_SERCOM_2_DMA
|
||||
#define DT_ATMEL_SAM0_I2C_SERCOM_2_DMA 0xFF
|
||||
#endif
|
||||
#ifndef DT_ATMEL_SAM0_I2C_SERCOM_3_DMA
|
||||
#define DT_ATMEL_SAM0_I2C_SERCOM_3_DMA 0xFF
|
||||
#endif
|
||||
#ifndef DT_ATMEL_SAM0_I2C_SERCOM_4_DMA
|
||||
#define DT_ATMEL_SAM0_I2C_SERCOM_4_DMA 0xFF
|
||||
#endif
|
||||
#ifndef DT_ATMEL_SAM0_I2C_SERCOM_5_DMA
|
||||
#define DT_ATMEL_SAM0_I2C_SERCOM_5_DMA 0xFF
|
||||
#endif
|
||||
#ifndef DT_ATMEL_SAM0_I2C_SERCOM_6_DMA
|
||||
#define DT_ATMEL_SAM0_I2C_SERCOM_6_DMA 0xFF
|
||||
#endif
|
||||
#ifndef DT_ATMEL_SAM0_I2C_SERCOM_7_DMA
|
||||
#define DT_ATMEL_SAM0_I2C_SERCOM_7_DMA 0xFF
|
||||
#endif
|
||||
|
||||
#define I2C_SAM0_DMA_CHANNELS(n) \
|
||||
.write_dma_request = SERCOM##n##_DMAC_ID_TX, \
|
||||
.read_dma_request = SERCOM##n##_DMAC_ID_RX, \
|
||||
.dma_channel = DT_ATMEL_SAM0_I2C_SERCOM_##n##_DMA,
|
||||
#define I2C_SAM0_DMA_CHANNELS(n) \
|
||||
.write_dma_request = ATMEL_SAM0_DT_INST_DMA_TRIGSRC(n, tx), \
|
||||
.read_dma_request = ATMEL_SAM0_DT_INST_DMA_TRIGSRC(n, rx), \
|
||||
.dma_channel = ATMEL_SAM0_DT_INST_DMA_CHANNEL(n, rx),
|
||||
#else
|
||||
#define I2C_SAM0_DMA_CHANNELS(n)
|
||||
#endif
|
||||
|
||||
#define DT_ATMEL_SAM0_I2C_SERCOM_IRQ(n, m) DT_ATMEL_SAM0_I2C_SERCOM_ ## n ## _IRQ_ ## m
|
||||
#define DT_ATMEL_SAM0_I2C_SERCOM_IRQ_PRIORITY(n, m) DT_ATMEL_SAM0_I2C_SERCOM_ ## n ## _IRQ_ ## m ## _PRIORITY
|
||||
|
||||
#define SAM0_I2C_IRQ_CONNECT(n, m) \
|
||||
do { \
|
||||
IRQ_CONNECT(DT_ATMEL_SAM0_I2C_SERCOM_IRQ(n, m), \
|
||||
DT_ATMEL_SAM0_I2C_SERCOM_IRQ_PRIORITY(n, m), \
|
||||
i2c_sam0_isr, DEVICE_GET(i2c_sam0_##n), 0); \
|
||||
irq_enable(DT_ATMEL_SAM0_I2C_SERCOM_IRQ(n, m)); \
|
||||
IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, m, irq), \
|
||||
DT_INST_IRQ_BY_IDX(n, m, priority), \
|
||||
i2c_sam0_isr, \
|
||||
DEVICE_GET(i2c_sam0_##n), 0); \
|
||||
irq_enable(DT_INST_IRQ_BY_IDX(n, m, irq)); \
|
||||
} while (0)
|
||||
|
||||
#if DT_INST_IRQ_HAS_IDX(0, 3)
|
||||
|
|
@ -795,67 +767,39 @@ static void i2c_sam0_irq_config_##n(struct device *dev) \
|
|||
#endif
|
||||
|
||||
#ifdef MCLK
|
||||
#define I2C_SAM0_CONFIG(n) \
|
||||
static const struct i2c_sam0_dev_config i2c_sam0_dev_config_##n = { \
|
||||
.regs = (SercomI2cm *)DT_ATMEL_SAM0_I2C_SERCOM_##n##_BASE_ADDRESS, \
|
||||
.bitrate = DT_ATMEL_SAM0_I2C_SERCOM_##n##_CLOCK_FREQUENCY, \
|
||||
.mclk = MCLK_SERCOM##n, \
|
||||
.mclk_mask = MCLK_SERCOM##n##_MASK, \
|
||||
.gclk_core_id = SERCOM##n##_GCLK_ID_CORE, \
|
||||
.irq_config_func = &i2c_sam0_irq_config_##n \
|
||||
I2C_SAM0_DMA_CHANNELS(n) \
|
||||
}
|
||||
#define I2C_SAM0_CONFIG(n) \
|
||||
static const struct i2c_sam0_dev_config i2c_sam0_dev_config_##n = { \
|
||||
.regs = (SercomI2cm *)DT_INST_REG_ADDR(n), \
|
||||
.bitrate = DT_INST_PROP(n, clock_frequency), \
|
||||
.mclk = (volatile uint32_t *)MCLK_MASK_DT_INT_REG_ADDR(n), \
|
||||
.mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, bit)), \
|
||||
.gclk_core_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, periph_ch),\
|
||||
.irq_config_func = &i2c_sam0_irq_config_##n \
|
||||
I2C_SAM0_DMA_CHANNELS(n) \
|
||||
}
|
||||
#else /* !MCLK */
|
||||
#define I2C_SAM0_CONFIG(n) \
|
||||
static const struct i2c_sam0_dev_config i2c_sam0_dev_config_##n = { \
|
||||
.regs = (SercomI2cm *)DT_ATMEL_SAM0_I2C_SERCOM_##n##_BASE_ADDRESS, \
|
||||
.bitrate = DT_ATMEL_SAM0_I2C_SERCOM_##n##_CLOCK_FREQUENCY, \
|
||||
.pm_apbcmask = PM_APBCMASK_SERCOM##n, \
|
||||
.gclk_clkctrl_id = GCLK_CLKCTRL_ID_SERCOM##n##_CORE, \
|
||||
.irq_config_func = &i2c_sam0_irq_config_##n, \
|
||||
I2C_SAM0_DMA_CHANNELS(n) \
|
||||
}
|
||||
#define I2C_SAM0_CONFIG(n) \
|
||||
static const struct i2c_sam0_dev_config i2c_sam0_dev_config_##n = { \
|
||||
.regs = (SercomI2cm *)DT_INST_REG_ADDR(n), \
|
||||
.bitrate = DT_INST_PROP(n, clock_frequency), \
|
||||
.pm_apbcmask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, pm, bit)), \
|
||||
.gclk_clkctrl_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, clkctrl_id),\
|
||||
.irq_config_func = &i2c_sam0_irq_config_##n, \
|
||||
I2C_SAM0_DMA_CHANNELS(n) \
|
||||
}
|
||||
#endif
|
||||
|
||||
#define I2C_SAM0_DEVICE(n) \
|
||||
static void i2c_sam0_irq_config_##n(struct device *dev); \
|
||||
I2C_SAM0_CONFIG(n); \
|
||||
static struct i2c_sam0_dev_data i2c_sam0_dev_data_##n; \
|
||||
DEVICE_AND_API_INIT(i2c_sam0_##n, \
|
||||
DT_ATMEL_SAM0_I2C_SERCOM_##n##_LABEL, \
|
||||
&i2c_sam0_initialize, &i2c_sam0_dev_data_##n, \
|
||||
&i2c_sam0_dev_config_##n, POST_KERNEL, \
|
||||
CONFIG_I2C_INIT_PRIORITY, &i2c_sam0_driver_api);\
|
||||
#define I2C_SAM0_DEVICE(n) \
|
||||
static void i2c_sam0_irq_config_##n(struct device *dev); \
|
||||
I2C_SAM0_CONFIG(n); \
|
||||
static struct i2c_sam0_dev_data i2c_sam0_dev_data_##n; \
|
||||
DEVICE_AND_API_INIT(i2c_sam0_##n, \
|
||||
DT_INST_LABEL(n), \
|
||||
&i2c_sam0_initialize, \
|
||||
&i2c_sam0_dev_data_##n, \
|
||||
&i2c_sam0_dev_config_##n, POST_KERNEL, \
|
||||
CONFIG_I2C_INIT_PRIORITY, \
|
||||
&i2c_sam0_driver_api); \
|
||||
I2C_SAM0_IRQ_HANDLER(n)
|
||||
|
||||
#if DT_ATMEL_SAM0_I2C_SERCOM_0_BASE_ADDRESS
|
||||
I2C_SAM0_DEVICE(0);
|
||||
#endif
|
||||
|
||||
#if DT_ATMEL_SAM0_I2C_SERCOM_1_BASE_ADDRESS
|
||||
I2C_SAM0_DEVICE(1);
|
||||
#endif
|
||||
|
||||
#if DT_ATMEL_SAM0_I2C_SERCOM_2_BASE_ADDRESS
|
||||
I2C_SAM0_DEVICE(2);
|
||||
#endif
|
||||
|
||||
#if DT_ATMEL_SAM0_I2C_SERCOM_3_BASE_ADDRESS
|
||||
I2C_SAM0_DEVICE(3);
|
||||
#endif
|
||||
|
||||
#if DT_ATMEL_SAM0_I2C_SERCOM_4_BASE_ADDRESS
|
||||
I2C_SAM0_DEVICE(4);
|
||||
#endif
|
||||
|
||||
#if DT_ATMEL_SAM0_I2C_SERCOM_5_BASE_ADDRESS
|
||||
I2C_SAM0_DEVICE(5);
|
||||
#endif
|
||||
|
||||
#if DT_ATMEL_SAM0_I2C_SERCOM_6_BASE_ADDRESS
|
||||
I2C_SAM0_DEVICE(6);
|
||||
#endif
|
||||
|
||||
#if DT_ATMEL_SAM0_I2C_SERCOM_7_BASE_ADDRESS
|
||||
I2C_SAM0_DEVICE(7);
|
||||
#endif
|
||||
DT_INST_FOREACH(I2C_SAM0_DEVICE)
|
||||
|
|
|
|||
|
|
@ -20,7 +20,19 @@ properties:
|
|||
clock-names:
|
||||
required: true
|
||||
|
||||
dma:
|
||||
type: int
|
||||
required: false
|
||||
description: DMA channel
|
||||
dmas:
|
||||
description: |
|
||||
Optional TX & RX dma specifiers. Each specifier will have a phandle
|
||||
reference to the dmac controller, the channel number, and peripheral
|
||||
trigger source.
|
||||
|
||||
For example dmas for TX, RX on SERCOM3
|
||||
dmas = <&dmac 0 0xb>, <&dmac 0 0xa>;
|
||||
|
||||
dma-names:
|
||||
description: |
|
||||
Required if the dmas property exists. This should be "tx" and "rx"
|
||||
to match the dmas property.
|
||||
|
||||
For example
|
||||
dma-names = "tx", "rx";
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue