drivers: i2c: i2c_sam0: rework devicetree support
Rework the devicetree to utilize new DT_INST macros and extract per instance data for clocks and dma from devicetree. We update the atmel,sam0-i2c binding for dma to replace the dma property with proper 'dmas' property. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
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2 changed files with 56 additions and 100 deletions
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@ -6,7 +6,6 @@
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#define DT_DRV_COMPAT atmel_sam0_i2c
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#include <errno.h>
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#include <device.h>
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#include <init.h>
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@ -733,48 +732,21 @@ static const struct i2c_driver_api i2c_sam0_driver_api = {
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};
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#ifdef CONFIG_I2C_SAM0_DMA_DRIVEN
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#ifndef DT_ATMEL_SAM0_I2C_SERCOM_0_DMA
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#define DT_ATMEL_SAM0_I2C_SERCOM_0_DMA 0xFF
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#endif
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#ifndef DT_ATMEL_SAM0_I2C_SERCOM_1_DMA
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#define DT_ATMEL_SAM0_I2C_SERCOM_1_DMA 0xFF
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#endif
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#ifndef DT_ATMEL_SAM0_I2C_SERCOM_2_DMA
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#define DT_ATMEL_SAM0_I2C_SERCOM_2_DMA 0xFF
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#endif
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#ifndef DT_ATMEL_SAM0_I2C_SERCOM_3_DMA
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#define DT_ATMEL_SAM0_I2C_SERCOM_3_DMA 0xFF
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#endif
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#ifndef DT_ATMEL_SAM0_I2C_SERCOM_4_DMA
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#define DT_ATMEL_SAM0_I2C_SERCOM_4_DMA 0xFF
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#endif
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#ifndef DT_ATMEL_SAM0_I2C_SERCOM_5_DMA
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#define DT_ATMEL_SAM0_I2C_SERCOM_5_DMA 0xFF
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#endif
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#ifndef DT_ATMEL_SAM0_I2C_SERCOM_6_DMA
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#define DT_ATMEL_SAM0_I2C_SERCOM_6_DMA 0xFF
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#endif
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#ifndef DT_ATMEL_SAM0_I2C_SERCOM_7_DMA
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#define DT_ATMEL_SAM0_I2C_SERCOM_7_DMA 0xFF
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#endif
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#define I2C_SAM0_DMA_CHANNELS(n) \
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.write_dma_request = SERCOM##n##_DMAC_ID_TX, \
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.read_dma_request = SERCOM##n##_DMAC_ID_RX, \
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.dma_channel = DT_ATMEL_SAM0_I2C_SERCOM_##n##_DMA,
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#define I2C_SAM0_DMA_CHANNELS(n) \
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.write_dma_request = ATMEL_SAM0_DT_INST_DMA_TRIGSRC(n, tx), \
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.read_dma_request = ATMEL_SAM0_DT_INST_DMA_TRIGSRC(n, rx), \
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.dma_channel = ATMEL_SAM0_DT_INST_DMA_CHANNEL(n, rx),
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#else
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#define I2C_SAM0_DMA_CHANNELS(n)
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#endif
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#define DT_ATMEL_SAM0_I2C_SERCOM_IRQ(n, m) DT_ATMEL_SAM0_I2C_SERCOM_ ## n ## _IRQ_ ## m
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#define DT_ATMEL_SAM0_I2C_SERCOM_IRQ_PRIORITY(n, m) DT_ATMEL_SAM0_I2C_SERCOM_ ## n ## _IRQ_ ## m ## _PRIORITY
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#define SAM0_I2C_IRQ_CONNECT(n, m) \
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do { \
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IRQ_CONNECT(DT_ATMEL_SAM0_I2C_SERCOM_IRQ(n, m), \
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DT_ATMEL_SAM0_I2C_SERCOM_IRQ_PRIORITY(n, m), \
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i2c_sam0_isr, DEVICE_GET(i2c_sam0_##n), 0); \
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irq_enable(DT_ATMEL_SAM0_I2C_SERCOM_IRQ(n, m)); \
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IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, m, irq), \
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DT_INST_IRQ_BY_IDX(n, m, priority), \
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i2c_sam0_isr, \
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DEVICE_GET(i2c_sam0_##n), 0); \
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irq_enable(DT_INST_IRQ_BY_IDX(n, m, irq)); \
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} while (0)
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#if DT_INST_IRQ_HAS_IDX(0, 3)
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@ -795,67 +767,39 @@ static void i2c_sam0_irq_config_##n(struct device *dev) \
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#endif
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#ifdef MCLK
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#define I2C_SAM0_CONFIG(n) \
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static const struct i2c_sam0_dev_config i2c_sam0_dev_config_##n = { \
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.regs = (SercomI2cm *)DT_ATMEL_SAM0_I2C_SERCOM_##n##_BASE_ADDRESS, \
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.bitrate = DT_ATMEL_SAM0_I2C_SERCOM_##n##_CLOCK_FREQUENCY, \
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.mclk = MCLK_SERCOM##n, \
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.mclk_mask = MCLK_SERCOM##n##_MASK, \
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.gclk_core_id = SERCOM##n##_GCLK_ID_CORE, \
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.irq_config_func = &i2c_sam0_irq_config_##n \
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I2C_SAM0_DMA_CHANNELS(n) \
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}
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#define I2C_SAM0_CONFIG(n) \
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static const struct i2c_sam0_dev_config i2c_sam0_dev_config_##n = { \
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.regs = (SercomI2cm *)DT_INST_REG_ADDR(n), \
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.bitrate = DT_INST_PROP(n, clock_frequency), \
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.mclk = (volatile uint32_t *)MCLK_MASK_DT_INT_REG_ADDR(n), \
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.mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, bit)), \
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.gclk_core_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, periph_ch),\
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.irq_config_func = &i2c_sam0_irq_config_##n \
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I2C_SAM0_DMA_CHANNELS(n) \
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}
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#else /* !MCLK */
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#define I2C_SAM0_CONFIG(n) \
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static const struct i2c_sam0_dev_config i2c_sam0_dev_config_##n = { \
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.regs = (SercomI2cm *)DT_ATMEL_SAM0_I2C_SERCOM_##n##_BASE_ADDRESS, \
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.bitrate = DT_ATMEL_SAM0_I2C_SERCOM_##n##_CLOCK_FREQUENCY, \
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.pm_apbcmask = PM_APBCMASK_SERCOM##n, \
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.gclk_clkctrl_id = GCLK_CLKCTRL_ID_SERCOM##n##_CORE, \
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.irq_config_func = &i2c_sam0_irq_config_##n, \
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I2C_SAM0_DMA_CHANNELS(n) \
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}
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#define I2C_SAM0_CONFIG(n) \
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static const struct i2c_sam0_dev_config i2c_sam0_dev_config_##n = { \
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.regs = (SercomI2cm *)DT_INST_REG_ADDR(n), \
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.bitrate = DT_INST_PROP(n, clock_frequency), \
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.pm_apbcmask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, pm, bit)), \
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.gclk_clkctrl_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, clkctrl_id),\
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.irq_config_func = &i2c_sam0_irq_config_##n, \
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I2C_SAM0_DMA_CHANNELS(n) \
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}
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#endif
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#define I2C_SAM0_DEVICE(n) \
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static void i2c_sam0_irq_config_##n(struct device *dev); \
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I2C_SAM0_CONFIG(n); \
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static struct i2c_sam0_dev_data i2c_sam0_dev_data_##n; \
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DEVICE_AND_API_INIT(i2c_sam0_##n, \
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DT_ATMEL_SAM0_I2C_SERCOM_##n##_LABEL, \
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&i2c_sam0_initialize, &i2c_sam0_dev_data_##n, \
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&i2c_sam0_dev_config_##n, POST_KERNEL, \
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CONFIG_I2C_INIT_PRIORITY, &i2c_sam0_driver_api);\
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#define I2C_SAM0_DEVICE(n) \
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static void i2c_sam0_irq_config_##n(struct device *dev); \
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I2C_SAM0_CONFIG(n); \
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static struct i2c_sam0_dev_data i2c_sam0_dev_data_##n; \
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DEVICE_AND_API_INIT(i2c_sam0_##n, \
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DT_INST_LABEL(n), \
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&i2c_sam0_initialize, \
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&i2c_sam0_dev_data_##n, \
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&i2c_sam0_dev_config_##n, POST_KERNEL, \
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CONFIG_I2C_INIT_PRIORITY, \
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&i2c_sam0_driver_api); \
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I2C_SAM0_IRQ_HANDLER(n)
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#if DT_ATMEL_SAM0_I2C_SERCOM_0_BASE_ADDRESS
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I2C_SAM0_DEVICE(0);
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#endif
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#if DT_ATMEL_SAM0_I2C_SERCOM_1_BASE_ADDRESS
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I2C_SAM0_DEVICE(1);
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#endif
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#if DT_ATMEL_SAM0_I2C_SERCOM_2_BASE_ADDRESS
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I2C_SAM0_DEVICE(2);
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#endif
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#if DT_ATMEL_SAM0_I2C_SERCOM_3_BASE_ADDRESS
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I2C_SAM0_DEVICE(3);
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#endif
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#if DT_ATMEL_SAM0_I2C_SERCOM_4_BASE_ADDRESS
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I2C_SAM0_DEVICE(4);
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#endif
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#if DT_ATMEL_SAM0_I2C_SERCOM_5_BASE_ADDRESS
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I2C_SAM0_DEVICE(5);
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#endif
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#if DT_ATMEL_SAM0_I2C_SERCOM_6_BASE_ADDRESS
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I2C_SAM0_DEVICE(6);
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#endif
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#if DT_ATMEL_SAM0_I2C_SERCOM_7_BASE_ADDRESS
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I2C_SAM0_DEVICE(7);
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#endif
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DT_INST_FOREACH(I2C_SAM0_DEVICE)
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@ -20,7 +20,19 @@ properties:
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clock-names:
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required: true
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dma:
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type: int
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required: false
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description: DMA channel
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dmas:
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description: |
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Optional TX & RX dma specifiers. Each specifier will have a phandle
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reference to the dmac controller, the channel number, and peripheral
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trigger source.
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For example dmas for TX, RX on SERCOM3
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dmas = <&dmac 0 0xb>, <&dmac 0 0xa>;
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dma-names:
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description: |
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Required if the dmas property exists. This should be "tx" and "rx"
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to match the dmas property.
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For example
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dma-names = "tx", "rx";
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