To avoid confusion, callbacks using ordinal pin numbers
is going to be reverted. So the driver has to be re-worked
to expose multiple devices so each device has 32 pins.
Also fixes#12765
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This allows the shared_irq driver to be configured by device tree.
With previous implementation, only the board configuration can
override the IRQ trigger, as the trigger config is a "choice" rather
than "config". With this patch, the driver can be fully configued at
the SoC level.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Actually, add the "status" property that enables the nodes explicitly.
They were apparently enabled by default without this property.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
From the driver point of view, monochrome controllers from the ssd16xx
family mostly differ by the amount of row and columns that are
supported. If they support more than 256 rows and/or columns the
corresponding size or position is sent using 2 bytes instead of 1 byte.
This patch therefore adds the width-bits and height-bits DT properties
to make this configurable.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Convert the hci_spi sample to get the SPI and GPIO settings from Device
Tree instead of Kconfig.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Use separate bindings for nRF Family SPI Slaves and SPI Masters so that
the properties "csn" and "def-char" can be made required for Slaves
(for Masters such settings are not applicable), and to avoid confusion
between the properties "csn" and "cs-gpios" for Master nodes.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Convert the HCI SPI driver to get the SPI and GPIO settings from Device
Tree instead of Kconfig. The "zephyr,bt-hci-spi" binding is used as
a common one for this purpose ("st,spbtle-rf" is removed), to take
advantage of the new DT_<COMPAT>_<INSTANCE> generated macros and get
rid of related fixups and aliases.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Use the new DT_<COMPAT>_<INSTANCE>_<PROP> defines to instantiate
devices. This commit adds also ability to define individual pin
locations on SoC series that support the feature. Definitions of GPIO
pins assigned to a given location have been moved from soc_pinmap.h file
to board DTS file.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
As we want to remove dts dependency on Kconfig, we had a case based on
CONFIG_BOOTLOADER_MCUBOOT. From a DTS point of view that was just
getting the chosen property 'zephyr,code-partition' set. We can easily
move this to the actual dts files and remove the mcuboot.overlay.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
spi,flash has been superseded by jedec,spi-nor so remove it.
atmel,at24 belongs in mtd rather than slave, so move it.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Use the new DT_<COMPAT>_<INSTANCE>_<PROP> defines to instantiate
devices. This commit adds also ability to define individual pin
locations on SoC series that support the feature. Definitions of GPIO
pins assigned to a given location have been moved from soc_pinmap.h file
to board DTS file.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Move IRQ number encoding out of dts_fixup.h and into the dtsi files.
For now just change devices on the dw_intc.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This board is unmaintained and unsupported. It is not known to work and
has lots of conditional code across the tree that makes code
unmaintainable.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Use the new DT_<COMPAT>_<INSTANCE>_<PROP> defines to instantiate
devices. This commit adds also ability to define individual pin
locations on SoC series that support the feature. Definitions of GPIO
pins assigned to a given location have been moved from soc_pinmap.h file
to board DTS file.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Support for HW flow control was recently enabled in the NXP MCUX
HAL layer. Let's add a DTS binding definition for "hw-flow-control".
The MCUX uart driver shim can use this to enable HW flow control.
Signed-off-by: Michael Scott <mike@foundries.io>
Convert ssd1306 display driver to use new defines so we can remove
the dts_fixup.h code for it. Also dropped "-i2c" from compatible.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert ssd1673 display driver to use new defines so we can remove
the dts_fixup.h code for it. Also dropped "-spi" from compatible.
Fix up references in reel_board dts and sample.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert the lpd880x driver to use device tree and new DT_<COMPAT>
defines. Support both LPD8803 & LPD8806 device tree compats.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add sam0_rtc_driver that implements system timer API on top of the RTC
and can be used as a replacement for the default systick timer.
Signed-off-by: Martin Benda <martin.benda@omsquare.com>
This commit introduces the possibility to have multiple
device nodes attached to the same I2S controller. For this
purpose a new i2s-device.yaml description has been introduced
with the a 'reg' property to define the logic number of the
device. For example, if two microphones are attached to the
same I2S port (say 1) to achieve stereo audio, the two microphones
might be described in dts as:
&i2s1 {
status = "ok";
mic@0 {
compatible = "...";
reg = <0>;
label = "...";
};
mic@1 {
compatible = "...";
reg = <1>;
label = "...";
};
};
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Fix the following dtc warnings on S1000:
Warning (simple_bus_reg): /soc/pinmux@81C30: simple-bus unit
address format error, expected "81c30"
Warning (alias_paths): /aliases: aliases property name must
include only lowercase and '-'
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Added UART4 alternate pin function for L4 µC for PC10 and PC11.
Corrected naming of previously defined UART4 TX and RX defines.
Signed-off-by: Georgij Cernysiov <g.cernysiov@elco-automation.de>
Adding a binding .yaml file for Nordic FICR and the
corresponding macro definition for NRF_FICR in
nrfx_config_nrf9160.h header file.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Correct the names of the binding files, so they comply
with binding file naming nomenclature.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit contributes a binding .yaml file for Nordic nRF
SPU peripheral and defines the macro for the peripheral base
register address in file ext/hal/nordic/nrfx_config_nrf9160.h.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add a level 2 interrupt controller for the RV32M1 SoC. This uses the
INTMUX peripheral.
As a first customer, convert the timer driver over to using this,
adding nodes for the LPTMR peripherals. This lets users select the
timer instance they want to use, and what intmux channel they want to
route its interrupt to, using DT overlays.
Signed-off-by: Marti Bolivar <marti@foundries.io>
Signed-off-by: Mike Scott <mike@foundries.io>
Add a Peripheral Clock Controller (PCC) driver. This gates and ungates
clocks to various peripherals on the SoC.
Signed-off-by: Michael Scott <mike@foundries.io>
Signed-off-by: Marti Bolivar <marti@foundries.io>
The OpenISA RV32M1 SoC has four CPU cores. Two of these are RISC-V
32-bit cores, which are named "RI5CY" and "ZERO-RISCY". (The other two
cores are ARM Cortex-M0+ and -M4.) This patch adds basic SoC
enablement for the RISC-V cores:
- basic dtsi, to be extended as additional drivers are added
- SoC definition in soc/riscv32/openisa_rv32m1 for RI5CY / ZERO-RISCY
- system timer driver for RI5CY, based on LPTMR0 peripheral
The timer driver will be generalized a bit soon once proper
multi-level interrupt support is available.
Emphasis is on supporting the RI5CY core as the more capable of the
two; the ZERO-RISCY SoC definitions are a good starting point, but
additional work setting up a dtsi and initial drivers is needed to
support that core.
Signed-off-by: Marti Bolivar <marti@foundries.io>
Signed-off-by: Michael Scott <mike@foundries.io>
We get the following warning:
extract_dts_includes.py: WARNING: id field set in
'SMSC/Microchip LAN9220 Ethernet controller', should be
removed.
Removed the id: field to fix.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The SPI1 controller that is connected to the mcr20a block utilizes the
hardware chipselect and not a GPIO CS. So remove the cs-gpios property.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The SPI0 node had a property called 'cs' which wasn't used or defined as
part of the binding yaml. So let's remove it.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
We get warnings from dtc when building any of the NXP i.MX-RT boards of
the form:
mimxrt1020_evk.dts_compiled: Warning (simple_bus_reg):
/soc/random@400CC000: simple-bus unit address format
error, expected "400cc000"
Simple fix to make everything lowercase to have the unit-address and reg
match.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Use auto-generated device tree macros in LIS2DH driver to avoid
usage of dts.fixup files. The triggered interrupt part has been
slightly hacked to automatically understand whether only int1 is
configured or both int1 and int2.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
