Commit graph

988 commits

Author SHA1 Message Date
Erwan Gouriou
cdd5856167 driver/gpio: stm32: Add STM32L5 support
Add basic GPIO support. Regarding interface with EXTI,
STM32L5 is similar to STM32G0.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-05-08 00:34:34 -05:00
Erwan Gouriou
f258199595 drivers/clock_control: Add clock_control on STM32L5 series
Add clock_control driver for STM32L5.
It's based on L4/WB driver since it is similar IP.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-05-08 00:34:34 -05:00
Erwan Gouriou
25ac59685f dts/arm/st: Add l5 device tree basics and stm32l552x socs
Add l5 secure and non secure device tree files

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-05-08 00:34:34 -05:00
Andrei Gansari
bfbbf92ad5 dts: nxp,lpc-rng binding and lpc55xxx RNG node
Binding used for LPC random number generator hardware.
Describes RNG device node in LPC5xxx SoCs device tree peripherals.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2020-05-07 23:25:31 -05:00
Francois Ramu
a08e262fa6 dts: arm: stm32wb: configure DMA and DMAMUX
This patch enables the DMA and DMAMUX on the stm32wb55x.
The DMAMUX has 14 channels.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2020-05-07 23:03:20 -05:00
Gerard Marull-Paretas
cfebfc188e drivers: adc: stm32: add support for H7 series
Add support for ADC on H7 series. Note that ADC1 and ADC2 share the same
register set, so it is added as "adc1_2".

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2020-05-07 23:01:59 -05:00
Kumar Gala
6ae8664889 drivers: i2s: i2s_sam_ssc: Convert to devicetree
Convert i2s_sam_ssc driver to utilize devicetree.  We replace Kconfig
options for specifying the DMA configuration (channel, DMA device name)
with getting that from devicetree.  We also get pincfg from devicetree,
however we still have Kconfig sybmols to specify if the RF or RK pin is
enabled.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-07 22:24:58 -05:00
Kumar Gala
49bab484df drivers: dma: sam_xdmac: Convert to devicetree
Convert sam_xdmac driver to utilize devicetree.  As part of the
controller binding we specify that dmas should contain a channel and the
perid for the DMA transaction.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-07 22:24:58 -05:00
Alex Porosanu
b1236954e8 boards: frdm_kw41z: enable PWM support
Once the TPM driver and the required configs have been added,
now this patch enables the usage of the PWM framework on KW41Z
SoCs. As such, the DTS gets the proper nodes and the pinmuxing
is done according to the configuration requested.

Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
2020-05-06 11:33:37 -05:00
Pete Johanson
91d6139338 boards: arm: nucleo_wb55rg: Enable USB for stm32wb.
* Define USB driver for base stm32wb device.
* Enable USB for the nucleo_wb55rg board.
* Properly initialize USB power + clock for the platform.

Signed-off-by: Pete Johanson <peter@peterjohanson.com>
2020-05-06 10:46:23 -05:00
Henrik Brix Andersen
25cf045b79 dts: arm: nxp: lpc55S1x: add hs_lspi device node
Add high-speed SPI controller device node to the NXP LPC55S1x SoC
series devicetree.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2020-05-05 17:03:29 -05:00
Henrik Brix Andersen
b782b2b7c6 dts: arm: nxp: lpc55S1x: include I2C devicetree header
Include the I2C devicetree header in the NXP LPC55S1x SoC series
devicetree.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2020-05-05 17:03:29 -05:00
Henrik Brix Andersen
521b28ecb4 dts: arm: nxp: lpc55S1x: fix interrupts properties for GPIO nodes
Fix the interrupt properties for GPIO nodes for the NXP LPC55S1x SoC
series.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2020-05-05 17:03:29 -05:00
Kumar Gala
dff8715615 drivers: ethernet: sam_gmac: rework pin config
Reworked sam_gmac driver to get pin ctrl/mux configuration information
from the device tree instead of via Kconfig and defines in soc_pinmap.h

We remove defines from soc_pinmap.h that are no longer needed due to
getting all that information from devicetree.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-04 11:32:10 -05:00
Stephanos Ioannidis
d2cd8a71bd dts: arm: atmel: Add MPU node for SAM D5x and E5x
The Atmel SAM D5x and E5x series SoCs include the ARM memory protection
unit that supports up to 8 memory regions.

This commit adds the missing device tree MPU node to `samd5x.dtsi`,
which is used by both the SAM D5x and E5x series SoCs.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-05-04 17:14:35 +02:00
Francois Ramu
28ff24d0ac dts: arm: stm32l4: configure dma instances
This patch is defining the DMA1 & 2 for the sm32l4 series
with 7 channels and support of mem2mem transfers

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2020-05-04 09:46:07 -05:00
Henrik Brix Andersen
f66d2fdd83 dts: nxp: k6x: add device tree node for DAC0 and DAC1
Add device tree nodes for the Digital-to-Analog (DAC) modules present
in the NXP Kinetis K6x series.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2020-05-01 12:35:50 -05:00
Henrik Brix Andersen
44144a2efe dts: nxp: ke1xf: add device tree node for DAC
Add device tree node for the Digital-to-Analog (DAC32) module present
in the NXP Kinetis KE1xF series.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2020-05-01 12:35:50 -05:00
Henrik Brix Andersen
a5d7946a73 dts: arm: nxp: add initial LPC55S16 devicetree
Add initial devicetree for the NXP LPC55S16. Only non-secure (ns)
access is supported for now.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2020-05-01 10:11:01 -05:00
Henrik Brix Andersen
9ceb29ac56 dts: introduce shared binding for the NXP FlexTimer
Do not assume in the SoC level device trees that NXP Kinetis FlexTimer
nodes will always be configured as PWM. Instead, configure FlexTimer
nodes for PWM at the board level for NXP Kinetis boards.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-04-30 08:28:48 -05:00
Kumar Gala
a918d301fe drivers: adc: adc_sam0: rework devicetree support
Rework the devicetree to utilize new DT_INST macros and extract per
instance data for clocks from devicetree.

We add a property ('calib-offset') for the SAM{D,E}5x family of SoCs
that is the bit position offset from ADC0 BIASCOMP in the NVM Software
Calibration Area Mapping.  For ADC0 this is typically 0 and for ADC1
this will be 14.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-29 08:02:36 -05:00
Erwan Gouriou
46649f9224 dts/bindings: st,stm32-can: Add optional master-can property
In STM32 can driver CAN2 instance need to know the base address
of CAN1 instance which is referenced as master can.
Add this information as an optional property to stm32 can binding.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-04-28 14:49:55 -05:00
Daniel Leung
13ef99831a drivers: gpio: mchp_xec: Convert to using new device tree macros
Convert driver to use the new device tree macro's instead of
dts_fixup.h based macros. This moves us closer to removing both
dts_fixup.h and per instance Kconfig symbols.

The pinmux_mchp_xec is also being updated since it's using DT
from GPIO.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-04-28 07:43:31 -05:00
Daniel Leung
5692702248 drivers: pinmux: mchp_xec: Convert to using new device tree macros
Convert driver to use the new device tree macro's instead of
dts_fixup.h based macros. This moves us closer to removing both
dts_fixup.h and per instance Kconfig symbols.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-04-28 07:43:31 -05:00
Kumar Gala
7a15afc1d4 drivers: flash: replace DT_FLASH_DEV_NAME with DT macro
Replace DT_FLASH_DEV_NAME with DT_CHOSEN_ZEPHYR_FLASH_CONTROLLER_LABEL.
We now set zephyr,flash-controller in the chosen node of the device
tree to the flash controller device.

NOTE: For a SoCs with on die flash, this points to the controller and
      not the 'soc-nv-flash' node.  Typically the controller is the
      parent of the 'soc-nv-flash' node).

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-27 18:43:20 -05:00
Alexandre Bourdiol
18a21920e4 dts\arm\st\g4: Fix ADC instances naming
ADC instances start with ADC_1
Fixes #24718

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2020-04-27 17:06:23 +02:00
Kumar Gala
fe573b6e23 dts: atmel: sam0: Add clocks for ADC and TCn devices
Add clock references for ADC and TC devices.  Update the bindings for
these devices to require clocks property and update the dtsi files to
have the clock info.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-25 13:33:56 -05:00
Kumar Gala
cb8ee73692 dts: atmel sam: Add pinctrl support for SAM SPI
Add pinctl support for the SAM SPI device.  We update the SPI
binding to have pinctrl-0 bindings that are expected to have
at least phandles for MISO, MOSI, and SPCK, but might also have
various chip selects as well.

The pinctrl nodes will have an 'atmel,pins' property that describes the
GPIO port, pin and periphal configuration for that pin.

We update sam*-pinctrl.dtsi files with all the various pin ctrl
configuration operations supported by the given SoC family.  These
files are based on data extracted from the Atmel ASF HAL
(in include/sam<FAMILY>/pio/*.h).

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-25 09:29:54 -05:00
Martí Bolívar
644f9ecbf0 dts: nordic: introduce wdt0 / wdt1 distinction
Add wdt0 node labels for all watchdogs. Keep the existing wdt node
labels in place for backwards compatibility.

Add a wdt1 node to the nRF5340 application core .dtsi, but leave it
disabled. Leave the wdt node's label set to "WDT" on this core for
backwards compatibility also, in case any users are getting it with a
string literal instead of asking the devicetree. This can be changed
later after this round of watchdog changes has been shaken out and
tested more.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2020-04-24 19:35:41 +02:00
Kwon Tae-young
15ed490df0 dts: arm: st: Add support for stm32l433Xb
Add support for the STM32L433Xb SoC.

Signed-off-by: Kwon Tae-young <tykwon@m2i.co.kr>
2020-04-24 06:36:35 -05:00
Stephanos Ioannidis
845d8852a5 dts: arm: atmel: samd5x: Fix CPU compatible
The SAM D5x and E5x series SoCs include the "Cortex-M4F" core, not the
FPU-less "Cortex-M4" core.

This commit fixes the incorrect CPU compatible for the SAM D5x and E5x
SoCs (note that this file is included by `same5x.dtsi`, which is used
as the base device tree header for the SAM E5x series).

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-04-24 06:27:58 -05:00
Gerson Fernando Budke
65c9b34abf soc: arm: atmel_sam: sam4s: Enable MPU
Add missing definitions to enable MPU support.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2020-04-24 10:16:10 +02:00
Gerson Fernando Budke
adcfd09b1b soc: arm: atmel_sam: sam4e: Enable MPU/FPU
Add missing definitions to enable MPU and FPU support.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2020-04-24 10:16:10 +02:00
Brian Kubisiak
fdf22d1072 arm: stm32f0: Add STM32F030XC support.
Add initial support for the stm32f030xc series of SoCs.

Signed-off-by: Brian Kubisiak <brian@kubisiak.com>
2020-04-24 09:56:46 +02:00
Kumar Gala
22e65cb9ba gpio: mcux: Convert convert to DT_INST defines
Convert driver to use DT_INST_ defines.  As part of this conversion we
remove the Kconfig options for per GPIO controller enables and instead
get that information from device tree.  This means we now disable each
GPIO controller by default in the DTS and have each board dts enable the
GPIO controller ports it needs.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-23 17:07:41 -05:00
Kumar Gala
94fcf2efa1 drivers: adc: adc_sam_afec: rework device tree support
Reworked adc_sam_afec driver to utilize new DT_INST macros as part of
this rework we also now get pin ctrl/mux configuration information
from the device tree instead of via Kconfig and defines in soc_pinmap.h

We remove defines from dts_fixup.h and soc_pinmap.h and associated
Kconfig symbols that are no longer needed due to getting all that
information from devicetree.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-23 06:11:26 -05:00
Kumar Gala
170d09b448 dts: atmel: sam0: Update dmac to be a proper dma controller
Move the atmel,sam0-dmac binding under the dma binding dir and add
cell information for channel and trigger source.  Update the associated
dtsi files to match these changes.

This is in prep of ATMEL SAM0 SERCOMM devices like UART, I2C, and SPI to
user proper 'dmas' property to specify the dma info to use.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-22 21:34:21 -05:00
Kumar Gala
8357005ba1 dts: atmel: sam0: Add initial clock devicetree support
Add support for the GCLK, MCLK, and PM clock controllers.  Add bindings
and devicetree nodes associated with these clock controllers.  Also add
clock references for the SERCOM peripheral set to allow those drivers
(i2c, spi, uart) to utilize this information.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-22 21:34:21 -05:00
Stephanos Ioannidis
7f2ddd371f dts: arm: atmel: Rename samd.dtsi to samd2x.dtsi
This commit renames `samd.dtsi` to `samd2x.dtsi` since this DTS header
is specific to the SAM D2x series and its derivatives (e.g. SAM R21).

Note that the SAM D5x series uses a different DTS header file (i.e.
`samd5x.dtsi`) due to the vast differences, and the future SAM D1x will
have to use a separate DTS header to be sensible anyway.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-04-22 13:13:38 +02:00
Kumar Gala
a54a2460d3 dts: arm: nxp: nxp_lpc55s6x: Fix sram ranges property
There was a typo bug in the SRAM ranges property that causes the SRAM
nodes to appear at the wrong addresses.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-21 17:40:37 -05:00
Kumar Gala
1b0e4124da dts: atmel sam: Add pinctrl support for SAM TWI and TWIHS I2C
Add pinctl support for the SAM TWI and TWIHS I2C devices.  We update
the TWI and TWIHS I2C bindings to have pinctrl-0 bindings that are
expected to have 2 phandles to the TWCK & TWD pinctrl nodes.

The pinctrl nodes will have an 'atmel,pins' property that describes the
GPIO port, pin and periphal configuration for that pin.

We update sam*-pinctrl.dtsi files with all the various pin ctrl
configuration operations supported by the given SoC family.  These
files are based on data extracted from the Atmel ASF HAL
(in include/sam<FAMILY>/pio/*.h).

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-21 15:46:30 -05:00
Kumar Gala
87186e5039 arm: nxp: imx-rt: default to PWMs being disabled in dts
Mark all the individual PWMs as disabled in dts and enable the one
explicitly used on the mimxrt1064_evk.dts in the board dts file.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-20 11:08:46 -05:00
Kumar Gala
1688d4b071 dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs
Have nodelabels match the SoC docs so when a nodelabel reference is
made in the code its easier to relate to the SoC.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-20 11:08:46 -05:00
Martin Jäger
414527926d drivers: dac: Add support for STM32L0 series
First implementation for STM32L0 series MCUs to be used for testing.

Signed-off-by: Martin Jäger <martin@libre.solar>
2020-04-20 17:41:48 +02:00
Takumi Ando
c2b2aad8ae soc: arm: stm32l1: Add UART4 and UART5 supports
Add UART4 and UART5 supports for STM32L1 series.

Signed-off-by: Takumi Ando <takumi@t15.red>
2020-04-20 15:54:22 +02:00
Erwan Gouriou
c2833af1af dts: stm32: Add generic compatible for flash controller
Add "st,stm32-flash-controller" as stm32 generic flash controller.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-04-20 03:51:36 -05:00
Kumar Gala
bdf58d11f0 dts: atmel sam: Add pinctrl support for SAM UART and USART
Add pinctl support for the SAM UART and SAM USART devices.  We update
the UART and USART bindings to have pinctrl-0 bindings that are expected
to have 2 phandles to the RX & TX pinctrl nodes.

The pinctrl nodes will have an 'atmel,pins' property that describes the
GPIO port, pin and periphal configuration for that pin.

We add sam*-pinctrl.dtsi files with all the various pin ctrl
configuration operations supported by the given SoC family.  These
files are based on data extracted from the Atmel ASF HAL
(in include/sam<FAMILY>/pio/*.h).

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-18 17:04:08 -05:00
Kumar Gala
ebbb92d330 dts: atmel sam: gpio: Add support for atmel,pins property
The atmel,pins property will be utilized to describe pin mux
configuration.  The property will be a phandle-array in which the
phandle points to the given GPIO port the pin is on, the pin number, and
the mux configuration.

This change updates the atmel,sam-gpio binding to support that
phandle-array and updates the associated SoC dtsi files as well.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-18 17:04:08 -05:00
Kumar Gala
3109981024 dts: arm: nxp: nxp_lpc55s6x: Remove GPIO2/3 nodes
GPIO2/GPIO3 don't exist on the lpc55s6x so remove these nodes and
associated aliases.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-17 10:16:40 -05:00
Kumar Gala
4f434b3bf2 dts: arm: nxp: nxp_lpc55s6x: Fix high speed SPI node
The flexcomm at 0x9f000 is a high speed SPI interface only.  Tweak the
device tree to reflect that.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-17 10:16:40 -05:00