The K64F SoC initialization previously used macros and structs
custom-defined in Zephyr in order to access peripheral registers.
Refactored it to use CMSIS-style register accesses from the ksdk
instead.
Change-Id: I80975c62de07ec95cf830e99cd5b0abb9623acd0
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The boot initialization and boot process of the sensor sub systems
is now using the new system log macros and updated the Kconfig
variable to be a level rather than a bool.
Change-Id: I098143684f8e7077a525e7fcbc93b42b22d427ac
Signed-off-by: Genaro Saucedo Tejada <genaro.saucedo.tejada@intel.com>
Reflects RAM increase that we get with SDK 0.8.2.
Change-Id: I5d7157834e29bb56864e81fedfb9766d5e4a24f8
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Previously, exception stubs had to be declared in assembly
language files. Now we have two new APIs to regsiter exception
handlers at C toplevel:
_EXCEPTION_CONNECT_CODE(handler, vector)
_EXCEPTION_CONNECT_NOCODE(handler, vector)
For x86 exceptions that do and do not push error codes onto
the stack respectively.
In addition, it's now no longer necessary to #define around
exception registration. We now use .gnu.linkonce magic such that
the first _EXCEPTION_CONNECT_*() that the linker finds is used
for the specified vector. Applications are free to install their
own exception handlers which will take precedence over default
handlers such as installed by arch/x86/core/fatal.c
Some Makefiles have been adjusted so that the default exception
handlers in arch/x86/core/fatal.c are linked last. The code has
been tested that the right order of precedence is taken for
exceptions overridden in the floating point, gdb debug, or
application code. The asm SYS_NANO_CPU_EXC_CONNECT API has been
removed; it was ill- conceived as it only worked for exceptions
that didn't push error codes. All the asm NANO_CPU_EXC_CONNECT_*
APIs are gone as well in favor of the new _EXCEPTION_CONNNECT_*()
APIs.
CONFIG_EXCEPTION_DEBUG no longer needs to be disabled for test
cases that define their own exception handlers.
Issue: ZEP-203
Change-Id: I782e0143fba832d18cdf4daaa7e47820595fe041
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
CONFIG_SOC_GENERIC_ARC doesn't exist so remove it.
Change-Id: Idecfd27684b5fd83b7b296daa46a1a21a0ae4d95
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
We have already done this on x86 and ARM. The policy is as follows:
* IRQ priority levels starting at 0 all have the same semantics and
do not have special properties. The priority level is either ignored
on arches which do not support programmable priority levels, or lower
priority levels take precedence over higher ones.
* Special-case priorty levels are specified via flags, in which case
the supplied priority level is ignored.
Issue: ZEP-60
Change-Id: Ic603f49299ee1426fb9350ca29d0b8ef96a1d53a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Created set of functions that was designed in the original RFC to
contain arch and soc specific code. This makes the interface to
the OS PM infrastructure cleaner and makes it easier to understand
the flow in the sample app. Also it makes code reuse easier across
soc/arch implementations. These are open to change in future if
other means to achieve the same goals are in place.
Jira: ZEP-227 ZEP-225
Change-Id: Ief57871c370341c55009ad4f456b7f71f2c2a3c6
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
The interrupt stack wasn't being initialized at boot.
Change-Id: Iec3e770d385643415641e15906c3a53f7c74a2e9
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Utilize the gcc -print-libgcc-file-name to determine the path to
libgcc.a. Using this also resolve issues if we are building with
floating point and the various ABIs to pickup the right lib.
We can also simply a few Makefiles and remove the need to export
_CROSS_COMPILE_arm_isa.
Change-Id: I293394c921c18fa4984173ba51825d6f9a333697
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Until now, EOI had always been sent out to the APIC with interrupts
unlocked. Depending on timing, there is a race where the next interrupt
on the same line could arrive before _IntExit disables interrupts
and pops context. If this happens consecutively enough times, the
interrupt stack will overflow.
Now we disable interrupts at the beginning of _IntExitWithEoi and they
remain that way until 'iret'.
Change-Id: Ibb28e0db902ff483d7a885389f231ac2d1864657
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Arches now select whether they want to use the GCC built-ins,
their own assembly implementation, or the generic C code.
At the moment, the SDK compilers only support builtins for ARM
and X86. ZEP-557 opened to investigate further.
Change-Id: I53e411b4967d87f737338379bd482bd653f19422
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This is at the expense of code size. The QEMU and MAX10
targets have plenty of space so enable it for these boards,
but leave off by default for others.
Change-Id: I93fdb7db14232727e9953b22490d8869ff3b60e7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The comments for INT_ACTIVE and EXC_ACTIVE now refer to
"executing context ..." for all architectures.
Change-Id: Ib868958639a3b30e1814fcaa4d1f0651d3b2561e
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
When CONFIG_SYS_POWER_DEEP_SLEEP is enabled, the _sys_soc_resume
function is called and the 'ZF' bit from EFLAGS register may be set
to 1. In that case, we end up wrongly jumping into 'copyDataDone'
label and no data is copied from ROM to RAM.
It seems this 'je' instruction is used without any previous comparison
operation which properly sets the ZF flag. Since 'ZF' initial value is
0, we never jump into 'copyDataDone' label. Also, this 'je' instruction
doesn't seem to be really required since, if %ecx is zero, no data will
be copied anyway.
That being said, this patch removes the 'je' instruction since it fixes
the bug described in the first paragraph and it doesn't affect the rest
of the crt0 execution.
Also, removes outdated information about section size and alignment.
Change-Id: Ia062b78247c4059009193a53f879aa1ebe80881d
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
Signed-off-by: Iván Briano <ivan.briano@intel.com>
The 16550 will now be the default console device.
Change-Id: I92a6b49984b055e7d5f5c97e5192150be0d5c5c7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We are not using this core build any more. Users should be using
the provided F core instead.
Change-Id: I2b5266273030c1bd355aafa78733b4077848d115
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This patch basically reverts patch "QMSI/uart: Use IOAPIC_EDGE instead
of IOAPIC_LEVEL". The issue with lost UART interrupts is fixed with
following patch: "_loapic_isr_vector_get: fix implementation" which is
a proper way.
Change-Id: I07aa168335827b09db7fcb2486b01585648ff5d6
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Some issues have been noted with nested interrupts on quark SE.
In particular, the wrong vector # being sent to the IOAPIC EOI
register. Now when doing EOI, we lock interrupts so that the act
of reading the current vector being serviced, and sending EOI
to both controllers happens atomically.
Change-Id: Id9ad992740e197bb9d4638764952b04a27c4af61
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The '_sys_soc_resume' symbol is function-type not data-type as declared
in crt0.S. This patch fixes this by using GTEXT macro instead.
Change-Id: Ibe8bcf92ab045bfe908fd2048d046083e773894f
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
The code expected r10 to be preserved across the call to the
event logger, which wasn't reasonable given that it is caller-
saved.
Change-Id: I694357ea7ee9b410b93b5a0894e8c38c53127363
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Having two parallel implementations is a maintenance issue, especially
when some strategically placed #ifdefs will suffice.
We prefer the ASM versions for SYS V, as we need complete control of
the emitted assembly for interrupt handling and context switching.
The SYS V code is far more mature. IAMCU C code has known issues with
-fomit-frame-pointer.
The only difference between the two calling conventions is that the
first three function arguments are provided in eax, edx, ecx instead
of on the stack.
Issue: ZEP-49
Change-Id: I9245e4b0ffbeb6d890a4f08bc8a3a49faa6d8e7b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Since we started to use UART_IRQ_FLAGS define them also for
quark_d2000 board. Note that we use IOAPIC_LEVEL since this is right
thing to do and the issue with lost interrupts is fixed in
_loapic_isr_vector_get().
Change-Id: Iaed0283bcc01290e420b42ff5d40ce9d99bfc677
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Use IOAPIC_EDGE instead of IOAPIC_LEVEL to fix missing interrupts.
During tests it was found that using IOAPIC_LEVEL interrupts for UART at
some points are lost.
Proposed by Calando, Antoine <antoine.calando@intel.com>
Change-Id: I18b20217c4d73fdeaa424bf59d00f6be1ec6ef1b
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
The emulator supports all the integer math instructions and has
the necessary registers for exception debugging.
Change-Id: I55938d9e3a4b9d219f6fee06fe070e860ca71d4b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
These are necessary to edit the CPU design in QSYS.
These originate from the F core archive supplied by Altera.
Change-Id: Ic03bd8738ae58dc154b5eaef91154fadaa61c491
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This build has support for hardware break/watch points.
Change-Id: Icf8a0d4abc82640eedd8c43322ebecf0ef069974
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We no longer assume pointer sizes are the same between host and
target, and use stdint defintions to size things.
Change-Id: Ie4dc41c60d62931fdb3d1764ade01c16a64d0b54
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Used by ARC, ARM, Nios II. x86 has alternate code done in assembly.
Linker scripts had some alarming comments about data/BSS overlap,
but the beginning of BSS is aligned so this can't happen even if
the end of data isn't.
The common code doesn't use fake pointer values for the number of
words in these sections, don't compute or export them.
Change-Id: I4291c2a6d0222d0a3e95c140deae7539ebab3cc3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We now allow use of -mgpopt=global and -mgpopt=data. The 'global'
option is now the default instead of compiler-default local, expanding
global pointer usage to all small data in the system.
For systems where all RAM is less than 64K, the 'data' option may be
appropriate.
Some fixes had to be made to the system in order to get around some
issues:
* prep_c.c no longer uses fake linker variables to figure out the size
of data or BSS, as these gave the linker fits as it tried to compute
relative addresses to them.
* _k_task_ptr_idle is create by sysgen and placed in a special section.
Any small data in a special section needs to be declared extern
with __attribute__((section)) else the compiler will assume it's in
.sdata.
* same situation with extern references to k_pipe_t (fixed pipe_priv
test)
For legacy applications being ported to Nios II which do things that
freak out global pointer calculation, it can be disabled entirely.
Change-Id: I5eb86ee8aefb8e2fac49c5cdd104ee19cea23f6f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
needs to be 0x8000 after .sdata and .sbss sections since
register offsets are 16-bit signed values.
Change-Id: Ia7486d32af81e54a6ebac6be7ec308dfdeafe79e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Adds Kconfig options CPU_HAS_FPU, FLOAT and FP_SHARING for the arm
architecture.
NOTE: All SOCs in the MK64F12 family have an FPU so that makes it a
convenient location to enable the hidden CPU_HAS_FPU option.
Change-Id: I71771d24f20f52079314bb8db9bf8a0aa827ab41
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Apply the correct compiler options when building for a Cortex-M4
processor that has floating point enabled. Using 'softfp' allows
floating point to be used with existing libraries supplied by the
Zephyr SDK. The 'hard' option would require new libraries to be
shipped with the SDK.
Change-Id: I141c20f54c2241134510888688637930c7b560a2
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
The caches get initialized on boot and flushed after XIP copy
takes place.
Change-Id: I642a14232835a0cf41e007860f5cdb8a2ade1f50
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Use all available ram, cut in half for simulated RAM/ROM
regions. Some larger test cases did not fit in 64K for
non-XIP case.
Change-Id: I12296286ca7efa5bcc1ceef30486c3fe8976811c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Interrupts and context switches are logged. Since this CPU does not
have a power-saving instruction, it never enters a sleep state so
we do not call _sys_k_event_logger_enter_sleep() from anywhere.
Change-Id: Idcef388e93ffea373446997a0f87e93a4db44331
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Interrupts must always be unlocked when coming out of this function
or execution will never leave _power_save() once entered.
Change-Id: Idda9d9be7cfc576a1072afec38000f63ae262a10
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Quark SE USB device (Designware IP) controller driver implements
the low level control routines to deal directly with the hardware.
Only FIFO mode supported.
Change-Id: I086186df017734579f0363ed79effc1481ff32c2
Signed-off-by: Adrian Bradianu <adrian.bradianu@windriver.com>
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
Enable floating point in the Cortex-M4 processor.
Change-Id: Ibadae12b9197d6486fd5c6a3d4e177fa9e1c71bc
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Saves and loads the non-volatile FP registers (s16-s31) when switching
between threads.
Change-Id: Ib3190452d9a70d722032ac83176eb4fbb92aca3d
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Adds the preemptive floating point registers to the ARM's thread
control structure.
Change-Id: I65fbee6303091ce0658bbc442c4707d306b68e92
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Updates the exception stack frame structure to include floating point
registers.
Change-Id: I0fef784cf4d91dda245180abd75bfd9221825fba
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
at91sam3 supposed to go to Sleep mode and stop the CPU clock
(HCLK). It leads to JTAG problems. In order to be able to use
JTAG, we need to keep CPU clock on. This is achieved by
switching to Wait mode and keeping external main clock.
Since Wait mode switches off automatically Fast RC Oscillator,
but keeps external clock untouched.
Change-Id: Ife37a7691c3cbdf434e560725a71d419adafe054
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
We are not going to handle unimplemented math instruction
exceptions at runtime. Remove remaining comments and exports
related to this. We don't need to leave a gap in the exception
stack frame for it either.
Change-Id: I4f1f3980a0e43bbf6f2f7488a9182f7acb06be05
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Before we were hard-coding them in the assembly file. Makes it
easier to alter the layout of the struct.
Change-Id: I619dc67c68ff87fe60de429a69b2f604292d270c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
