The faulting instruction was off by 4 bytes and we weren't printing
the exception cause code properly.
Change-Id: I86f4320c7be43dca96940186def56aa5e47bc49f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We want to pass along the stack pointer, not dereference it.
Change-Id: I554eff316bffe50654942746e7960b561abb413b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Pulled from the ARC implementation. Tested via
test_obj_tracing.
Change-Id: I858e89cc9187f99539b362ade8098b3606d31464
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The extra and redundant -serial was casuing issues, remove.
Pass -nographic to work around issues with the experimental QEMU
builds.
Change-Id: I3102fe026a56781d5c4fb20acaa519af368f8a41
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Unnecessary and generates build errors for microkernel.
Change-Id: I678f44aa2b68c8f8954c78e7828e534f0c1f4215
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
It's all RAM, but we pretend the range 0x410000 - 0x420000
is the "ROM" region, and stuff gets copied into RAM starting
at 0x400000.
Change-Id: Idf6bd603e2552593f588cf6130ee4da946bcf5a3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Nios II CPUs vary in configuration on whether they support
'mul', 'mulx', and 'div' family of instructions. The compiler
can be told to use GCC integer library routines instead if
needed.
Ideally we would just pull the configuration out of system.h,
but pulling include file #defines into the Make environment
will involve some build system work that is best left to a
later improvement.
We've decided to take this build-time approach rather than
handle unimplemented instruction exceptions, so remove the
hook in exception.S
Change-Id: I05be0d5ed4c1a49b23dca1550ee66fd5891044d2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
If the CPU lacks certain features the only writable bit in the
status register is the PIE bit, so just write the saved value back.
Change-Id: I91537ff640aa9977d19587c4b0ae414028752341
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
No longer necessary as all the stubs which didn't use their
parameters have now been implemented.
Change-Id: I0ab3f024431426fbdac6d17de21e9c7338879f6e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The return value of _Swap() is often treated as a "don't care" value and thus
often ignored. However, there are cases when it is desirable to have a
meaningful return value. This meaningful value can be assigned via
fiberRtnValueSet(). To that end, a new field has been added to the coop
register struct to store this value for when _Swap() needs to return that
meaningful value.
Change-Id: Ic4967fa7d602850c09ebde18e8bfd4c97cda9ec8
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
For this implementation, the presence of a value in global
_offload_routine signifies to the exception code that we should
enter the IRQ handling code even if there are no bits enabled
in ipending. The 'trap' instruction gets us into the exception
handling code.
Change-Id: Iac96adba0eaf24b54ac28678a31c26517867a4d2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We check to see if the stack pointer is somwhere on the
interrupt stack.
Change-Id: Ic9d21e9f03476b9c8955c44cbfa2e61dd1daed22
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Required by microkernel, currently does nothing.
Change-Id: I256886e3a52817d9216599bbf5691bc27c1d0ad8
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Per Altera these files for the /F core are freely distributable.
README included with instructions and links to necessary software.
Origin: Altera
Change-Id: I58c0dbcb5a2b11f0845d4e390e6aa0020d8b3ed5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This is a workaround until we can modify the kernel to pull this
value out of system.h instead of Kconfig.
Change-Id: Iaafa9003d2bbcb5b38a050c371466a206f716ae7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Supports Internal Interrupt Controller only for now; EIC
supoort tracked in ZEP-258.
Change-Id: I2d9c5180e61c06b377fce4bda8a59042b68d58f2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
With this code we can successfully boot and context switch into
the main thread. Nanokernel hello_world has the expected
"Hello World!" string in the RAM console.
Change-Id: I56335d992f5a7cbb12d9e4c02d1cc23ea28ae6ef
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
If XIP is turned on, only hardware breakpoints may be used, and
code cannot be loaded onto the device with nios2-download
or GDB 'load' command. RAM-constrained applications are free to
enable this if they need to.
Change-Id: Iee2d41f71f7ca2bc599801cf3cf0fac680273e51
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
When an image is sent over the wire with the GDB 'load' command,
it tries to start execution from the __start symbol, which needs to
be in RAM. Since the reset vector is in ROM, name it something else.
Change-Id: Id0bbfa76db9a8a81bd7ff20be3f2baec81eae15e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Kconfig doesn't enforce any kind of alignment when specifying the
ISR stack size. Perform the assembly equivalent of STACK_ROUND_DOWN.
Change-Id: Ib7fb72ff7db8a3aa20ec6d0c59a03aa8227f6671
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
CONFIG_INIT_STACKS should initialize all stack regions
with 0xaa. Make sure the initial interrupt stack gets this
as well. Take care not to exceed the bounds of the array
if it is not 4-byte aligned.
Change-Id: Ib23329ac84a5a8515272be2944f948e8faba65b3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This core has extra debugging features useful for this bring-up
exercise.
Change-Id: I619bc8768acb1d9be8699a6e238168f47e605f3d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Add hidden configuration HAS_KSDK for SoCs to select if they have
support in the ksdk.
Change-Id: Ia4cd11901bc26d21a3bdfad6236d66656bb292cb
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Use a kbuild trick to force built-in.o to get built even if there isn't
any code so we can link properly. This is cleaner than keeping around
empty files that don't do anything.
Change-Id: I4214d21104fe5f49613fa5697c8116b0e8c8aa50
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
There was a reference to SOC_FAMILY_NRF5 which was not use by anyone
else and it seemes like it was a typo, where the right reference was
to symbol SOC_NRF5. However, the right fix is to move both sites to
use SOC_FAMILY_NRF5 *and* fix the SOC_SERIES to be only nrf52,
otherwise it causes path duplication and the build fails.
This was also causing documentation warnings that are thus killed.
Change-Id: I92e74a6158f02df43e6e857df8f1e67bcfdd9551
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
Change the LOAPIC timer IRQ number to 10. It should not
be 0.
Change-Id: I156286d0e3b903cca07cc3f87804b145aacaf117
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
The ReST parser dislikes enumerations with no empty lines in
between. Whatever.
Change-Id: I480c08fe5b69f0d0f3ebfacdc64fc9e3ec94da21
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
No code uses it and it being undefined anywhere generates a
documentation warning.
Change-Id: I09de2e58edf82e7fb9780a5dea98a282502436b6
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
The KSDK device header files require a preprocessor macro that defines
the part number string (e.g., MK64FN1M0VMD12). Create a hidden Kconfig
option to hold the part number string, and hidden Kconfig options that
the board Kconfig will use to select the specific part number.
Change-Id: I612e785026261e425b47b5b7fae0c65b4f94b30b
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
We get these out of system.h instead. A clause in libc-hooks.c
for newlib added since we don't get RAM size from
CONFIG_SRAM_BASE_ADDRESS.
Change-Id: Ic35113395b951f625e8e29658afe19c525037964
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We will require 6 variables to be defined by SOC-specific
linker script; these values in turn can be pulled from
defines in layout.h.
To help position code correctly we define two new ELF sections
for this arch, 'reset' and 'exceptions'.
Change-Id: Idffbd53895945b7d0ec0aac281e5bf7c85b4b2c2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Nios II does not have a power saving instruction, so there is nothing
to really do here other than ensure that interrupts are in the correct
state when leaving nano_cpu_atomic_idle().
Change-Id: I664c7542dc2fc1795a453d35e183a737dcb20c38
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
For the moment, NIOS2_CPU_SOF must be set with the path to the
CPU configuration. We are checking with Altera on whether we
can directly check in the binary to the source tree.
These scripts depend on tools provided by the Altera Quartus
Prime Lite Edition. This is available for free but requires
registration on Altera's website to obtain.
Change-Id: Ia6cb6c9e43c3e141807a887cb25c47b370a7d8e9
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Altera tools for creating .pof files for flashing onto their
FPGAs require UFM data to be in this special format. Extend
the current 'all' and 'zephyr' targets to additionally create
this .hex file using objcopy, with the same exclusions as the
existing rule for .bin files.
Change-Id: I75293fba47536545359f817a1f2c1ae905b9d25c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
__start is the CPU's reset vector. In a typical Nios II configuration,
the exception vector is 0x20 bytes after the reset vector, severely
constraining the amount of code that can go in here.
Split this into __start and __text_start. The only thing that __start
really need to do is init the instruction cache and jump into
__text_start.
JIRA IDs placed in comments for missing items.
Change-Id: I3c6b8ed65e8fcf6b6a735b80cf007d0180599230
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Linker scripts for Nios II will also need these headers as it
specifies the device's physical layout and various important
vector addresses.
Change-Id: Ie9efaf19e53d2493eed7b9783052393d7ea9dd0f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Include nrf.h instead of directly using the specific header
required. This will be useful in the future when additional
Nordic ICs are supported.
JIRA: ZEP-377
Change-Id: I7a7257b0aaa5fa0a0d202322c366efbdd1d84458
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Translate CONFIG_SOC_SERIES_NRF52X to NRF52, which is the macro
expected by the Nordic MDK headers.
JIRA: ZEP-377
Change-Id: Ic846e4cddf8146ae9d96bc98d4b12311552dc4f6
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
There are a few problems with the code being repaired here.
1. A seti was used to re-enable all interrupts, even though the
thread being switched to may have had certain interrupt priorities masked.
2. saved status32 already has SC bit if thats wanted, so its ok to just
restore status32 as-is w/o needing to and off anything.
3. the code is difficult to write using kflag and seti because as you
restore registers, there aren't any to use. But we can exploit a
trick where we pretend an interrupt has occured by setting a bit in
AUX_IRQ_ACT, and then use RTIE instruction to restore status32
atomically with branching to return address. Something about the way
this code was written was causing stack corruptings and crashes in an
application that uses a high rate of both FIRQ and Regular interrupts.
Change-Id: Ia7166d51f0e750c07832ab115b7151ce37ee0278
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Since firq utilizes a 2nd register bank, and since all of those
many GPRs can be used, the strategy here is to save extra registers,
such as lp_count, lp_start, lp_end into callee saved registers.
These registers are safe to use because the C-ABI followed by the
compiler will cause these to be spilled to the stack if a C function
wants to use them. By selecting upper GPRs, r23-r25, it is very unlikely
the compiler will spill them. This improvement, therefore, can avoid a
d-cache miss since we are avoding memory altogether when saving these.
The struct firq_regs is no longer needed.
Change-Id: I7c0d061908a90376da7a0101b62e804647a20443
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Generate kernel image in Intel Hex format when building for the nRF52.
Remove the additional step from the board doc file.
Change-Id: I619496f64037c2a0ac459ae05e549e01458e0f71
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
It was found that the test latency_measure, when compiled
for microkernel, would fail on the ARC. This because the
trap handler, used by irq_offload, wasn't supporting thread switching.
This submission adds the code to do that, and the code size is
bigger only when CONFIG_MICROKERNEL is defined.
To keep code a bit smaller, there is a trick exploited here where
the AE bit is cleared in the STATUS32 register and in AUX_IRQ_ACT,
bit 1 is set, to make it appear as if the machine has interrupted
at priority 1 level. It then can jump into some common interrupt
exit code for regular interrupts and perform an RTIE instruction
to switch into the new thread.
test/latency_measure/microkernel now passes.
Change-Id: I1872a80bb09a259814540567f51721203201679a
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
