Commit graph

3814 commits

Author SHA1 Message Date
Wayne Ren
7ef2506611 arch: arc: enable US bit to check user mode
Enable us bit to check user mode more efficienly.

US is read as zero in user mode. This will allow use mode sleep
instructions, and it enables a form of denial-of-service attack
by putting the processor in sleep mode, but since interrupt
level/mask can't be set from user space that's not worse than
executing a loop without yielding.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-16 12:20:16 +01:00
Wayne Ren
8feca6c2ef arch: arc: modify the kconfig for mpu case
* user space support requires THREAD_INFO
* for MPU version 2, the stack align is at least 2048 bytes
  * the smallest mpu region is 2048 bytes
  * the region size must bt power of 2
  * the start address of region must be aligned to the region size

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-16 12:20:16 +01:00
Wayne Ren
e91733c78b arch: arc: bug fixes and add user space support in secure mode
* bug fixes
* add user space support in secure mode

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-16 12:20:16 +01:00
Wayne Ren
f81dee0b2b arch: arc: add user space support for arc
* add the implementation of syscall
  * based on 'trap_s' intruction, id = 3
* add the privilege stack
  * the privilege stack is allocted with thread stack
  * for the kernel thread, the privilege stack is also a
    part of thread stack, the start of stack can be configured
    as stack guard
  * for the user thread, no stack guard, when the user stack is
    overflow, it will fall into kernel memory area which requires
    kernel privilege, privilege violation will be raised
* modify the linker template and add MPU_ADDR_ALIGN
* add user space corresponding codes in mpu
* the user sp aux reg will be part of thread context
* When user thread is interruptted for the 1st time, the context is
  saved in user stack (U bit of IRQ_CTLR is set to 1). When nest
  interrupt comes, the context is saved in thread's privilege stack
* the arc_mpu_regions.c is moved to board folder, as it's board
  specific
* the above codes have been tested through tests/kernel/mem_protect/
  userspace for MPU version 2

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-16 12:20:16 +01:00
Anas Nashif
8949233390 kconfig: fix more help spacing issues
Fix Kconfig help sections and add spacing to be consistent across all
Kconfig file. In a previous run we missed a few.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-02-15 23:20:55 -05:00
Carles Cufi
f24f50b12e arm: cortex_m: Use new ARMV6_M_ARMV8_M_BASELINE in vector relay
The old ARMV6_M Kconfig option has been removed, and so to correctly set
the dependencies for SW_VECTOR_RELAY we need to use the new
ARMV6_M_ARMV8_M_BASELINE.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-02-14 12:49:09 +01:00
Andy Gross
4c47d7f7e2 arch: arm: Enable stack guard before starting main
This patch fixes a hole in the stack guard configuration.  The initial
branch to main is missing the stack guard configuration.

Fixes: Issue #3718

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-13 13:06:41 -08:00
Andy Gross
465e04cae7 arch: arm: Fixup stack end calculations
This patch fixes calculations for the top of the interrupt and main
stacks.  Due to power of two alignment requirements for certain MPUs,
the guard size must be taken into account due to the guard being
counted against the initial stack size.

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-13 12:42:37 -08:00
Andy Gross
f7ec62eb85 arm: mpu: Enable userspace support for NXP and ARM
This patch set implements the APIs and changed required to support
the user mode thread support.

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-13 12:42:37 -08:00
Andy Gross
1c047c9bef arm: userspace: Add ARM userspace infrastructure
This patch adds support for userspace on ARM architectures.  Arch
specific calls for transitioning threads to user mode, system calls,
and associated handlers.

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-13 12:42:37 -08:00
Andy Gross
9ccdcb9be6 arm: mpu: Add user context API placeholder
This patch adds a configure_mpu_user_context API and implements
the required function placeholders in the NXP and ARM MPU files.

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-13 12:42:37 -08:00
Michael Scott
7a9b688526 x86: fix build warning
During compile of lwm2m_client using qemu_x86, the following build
warning was noticed:
zephyr/arch/x86/core/excstub.S:132:2: warning: "/*" within comment [-Wcomment]
  /*

In commit ff42bdd0a0 ("debug: remove option GDB_INFO"), the comment tag
was omitted.  Fix the comment end tag.

Signed-off-by: Michael Scott <michael@opensourcefoundries.com>
2018-02-12 19:21:06 -05:00
Anas Nashif
11a9625eaf debug: remove DEBUG_INFO option
This feature is X86 only and is not used or being tested. It is legacy
feature and no one can prove it actually works. Remove it until we have
proper documentation and samples and multi architecture support.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-02-12 13:58:28 -08:00
Anas Nashif
ff42bdd0a0 debug: remove option GDB_INFO
This feature is X86 only and is not used or being tested. It is legacy
feature and no one can prove it actually works. Remove it until we have
proper documentation and samples and multi architecture support.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-02-12 13:58:28 -08:00
Sean Nyekjaer
a09b6f538a arch: atmel_sam0: rename samd SoC series to samd21
Atmel SAMD21 series was classified too broadly as SAMD.
This patch names it correctly to make room,
for other members of SAMD series

Signed-off-by: Sean Nyekjaer <sean@nyekjaer.dk>
2018-02-09 08:34:55 -06:00
247782a7b3 sam0: move the UART and SPI configuration into pinmux.
Also pull out the SERCOM pads configuration to defines.  Note that the
SAM0 has a two level configuration - a signal (like TX) is mapped to a
pad, and then a pad is mapped to a function on a pin.

Signed-off-by: Michael Hope <mlhx@google.com>
2018-02-08 12:09:46 -06:00
Ioannis Glaropoulos
0d6fa4db0a arch: arm: define Cortex-M23, Cortex-M33 CPUs
This commit defines the Kconfig options for
ARM Cortex-M23 and Cortex-M33 CPUs. It also
udpates the generic memory map for M23 and M33
implementations.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-02-08 12:07:38 -06:00
Ioannis Glaropoulos
a0a03d7597 arch: arm: common Armv8-M support
This PR includes the required changes in order to support
conditional compilation for Armv8-M architecture. Two
variants of the Armv8-M architecture are defined:
- the Armv8-M Baseline (backwards compatible with ARMv6-M),
- the Armv8-M Mainline (backwards compatible with ARMv7-M).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-02-08 12:07:38 -06:00
Savinay Dharmappa
98d6a9928c driver: usb_dw: Move base address and irq num of usb to soc.h
base adrress and irq number moved to soc.h

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-02-07 22:55:11 -05:00
Ramakrishna Pallala
3eb62bc905 drivers: i2c: Add i2c master driver for Nios-II i2c core
Add I2C Master driver for Nios-II I2C soft IP core.

This driver relies upon the Altera HAL I2C driver for all the bus level
transactions, interrupt handling and register programming.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-02-07 19:37:35 -05:00
Alberto Escolar Piedras
3b924ede3e native: coverage exclusions
Just some exclusions to coverage in code which cannot be
reached, or can only be reached in error conditions

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-02-07 16:28:16 -05:00
Alberto Escolar Piedras
66c1652fb8 native: native_posix timer + irq fix
Added possibility to reconfigure CONFIG_SYS_CLOCK_TICKS_PER_SEC
for the native_posix board (before it could only be 100)
+
Fixed tickless idle support
+
Minor fixes in irq wrapping

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-02-07 16:28:16 -05:00
Alberto Escolar Piedras
a99a14c3b7 native: added posix_get_hw_cycle()
Added function (for all ARCH_POSIX boards) to get the
the current clock cycle of the CPU

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-02-07 16:28:16 -05:00
David B. Kinder
c2bf3af1de doc: fix misspellings in Kconfig files
Missed some misspellings during regular reviews.

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2018-02-07 14:51:46 -05:00
Carles Cufi
4b23b5d589 arch: arm: Do not enable SW_VECTOR_RELAY with M0+ and VTOR
Whenever a Cortex-M0+ supports the VTOR register it makes no sense to
use the software vector relay mechanism. Therefore change the logic so
that SW_VECTOR_RELAY does not get enabled whenever a VTOR register is
present, but enable it if an M0+ has no VTOR.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-02-07 07:31:32 -06:00
Rajavardhan Gundi
1e6adba9ef drivers/interrupt_controller: Introduce multi-level interrupt support
In a scenario where a platform harbours multiple interrupts to the
extent the core cannot support it, an interrupt controller is added
as an additional level of interrupt. It typically combines several
sources of interrupt into one line that is then routed to the parent
controller.

Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
2018-02-06 22:39:05 -05:00
Gil Pitney
3f68f2bc97 soc: ti_simplelink: cc32xx: Remove ARMV7_M guard from CMSIS_IRQn_Type
Remove unnecesary #ifdef CONFIG_ARMV7_M guard in soc.h file.

Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2018-02-06 17:34:25 -06:00
Chunlin Han
18560a01a4 arm: Generate privileged stacks
This patch adds the generation and incorporation of privileged stack
regions that are used by ARM user mode threads.  This patch adds the
infrastructure for privileged stacks.  Later patches will utilize the
generated stacks and helper functions.

Signed-off-by: Chunlin Han <chunlin.han@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-06 15:31:16 -08:00
Andy Gross
e8860fe8be arm: Add app data section alignment constraints
This patch adds application data section alignment constraints
to match the region definition requirements for ARM MPUs.  Most MPUs
require a minimum of 32 bytes of alignment for any regions, but some
require power of two alignment to the size of a region.

This requires that the linker align the application data section to
the size of the section.  This requires a linker pass to determine the
size.  Once this is accomplished the correct value is added to a linker
include file that is utilized in subsequent linker operations.

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-06 15:31:16 -08:00
Andy Gross
65ac049105 kernel: arm: core: Fix thread monitor wrapping
This fixes the wrapping of the thread monitor specific parts of the
new thread code.

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-06 15:31:16 -08:00
Erwan Gouriou
c734c2972f flash: remove obsolete FLASH_DRIVER_NAME
Replace seldom occurrences of FLASH_DRIVER_NAME by equivalent
and commonly used FLASH_DEV_NAME.

Fixes #5919.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2018-02-06 11:48:53 -06:00
Ilya Tagunov
d2b09497eb arm: core: cortex_m: introduce CPU_CORTEX_M_HAS_VTOR option
Some ARMv6-M Cortex-M0+-based SOCs have VTOR register
and can relocate vector table just as ARMv7-M ones.
Vector table relocation path should be choosed
by VTOR presence, not by arch.

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2018-02-06 08:59:36 -06:00
Yannis Damigos
5d3016aa65 boards: arm: stm32f3_disco: Enable SPI_1, SPI_2 ports
Enable SPI1 and SPI2 ports on stm32f3_disco.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-02-05 09:21:33 -06:00
Ramakrishna Pallala
c02a2bed61 drivers: flash: Add Nios-II QSPI flash driver
Add Altera Nios-II QSPI Flash controller driver which has
has 1024 blocks or sectors wich each sector size being 64K bytes.
This driver supports flash erase, write, read and lock operations.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-02-05 06:30:50 -08:00
Alberto Escolar Piedras
fb442b0d9a native: exclude from coverage not coverable code
Some code in the POSIX architecture is only meant to handle
safely errors which should never occur and therefore
are not covered.
=> We exclude them from the coverage reports.

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-02-05 06:26:53 -08:00
Alberto Escolar Piedras
c53924cfe9 native: SOC: exclude unlikely code from coverage
Some code in the POSIX SOC (inf_clock) will only be executed
if the program is terminated by receiving a SIGTERM in a particular
part. Therefore to avoid confusing developers with changing
coverage, let's exclude it from the coverage reports.

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-02-05 06:26:53 -08:00
Alberto Escolar Piedras
d9e1182f3a native: POSIX arch: Exclude unlikely code from coverage
Some code in the POSIX arch core will only be executed
in some very atypical cases depending on the host load.
To avoid confusing developers, let's exclude it from the
coverage reports.

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-02-05 06:26:53 -08:00
Alberto Escolar Piedras
a7e55b82dd native: arch: added recommended stack size config
Added a new config variable with the recommended stack
size for threads which are only meant for the posix architecture

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-02-02 07:48:46 -08:00
Yannis Damigos
6a6a4294c2 boards: arm: olimexino_stm32: Enable SPI1 port
Enable SPI1 port on olimexino_stm32.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-02-01 08:19:49 -06:00
Yannis Damigos
af0c9fc349 drivers: spi_ll_stm32: Enable SPI driver for F1 family
Enables SPI driver for STM32F1 SoCs

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-02-01 08:19:49 -06:00
Anas Nashif
9a238cd538 soc: atom: support enumerating PCI devices
This hook is needed to support enumerating PCI devices.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-02-01 02:19:45 -05:00
Maureen Helm
d107411820 arm: nxp_kinetis: Define FLASH_DRIVER_NAME macro for kl2x and kwx SoCs
Defines the FLASH_DRIVER_NAME macro in soc.h for kinetis kl2x and kwx
SoC series. This macro is used by the storage and dfu subsystems, as
well as the flash_shell sample.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-01-31 16:43:40 -06:00
Ramakrishna Pallala
301acb8e1b kernel: include: rename nano_internal.h to kernel_internal.h
Rename the nano_internal.h to kernel_internal.h and modify the
header file name accordingly wherever it is used.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-01-31 10:07:21 -06:00
Alberto Escolar Piedras
a35364dd1a native: minor consistency rename
rename main_clean_up() to posix_exit() for consistency
with all other global functions of this architecture

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-01-29 23:23:56 -05:00
Adithya Baglody
77755afa19 userspace: ARM: Fixed Kconfig for ARM_USERSPACE
Currently in zephyr the support for the arm userspace has not be
merged. But the Kconfig always sets the userspace flag and causes a
build failure. This is blocking the test cases for userspace.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-01-29 23:11:11 -05:00
Carles Cufi
7361d3d74d config: bootloader: Add support for MCUboot
Add a new Kconfig option, BOOTLOADER_MCUBOOT, that automatically sets
the required options necessary to make the resulting image bootable by
the MCUboot open source bootloader. This includes the text section
offset and the vector relay table for Cortex-M0, and in the future it
might also add the DTS overlay required to link at slot0 offset in
flash.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-01-29 18:05:18 -05:00
Kumar Gala
b8173d960e drivers: flash: NXP KL2X/KW4xZ: Add device tree support
Add device tree support for the "nxp,kinetis-ftfa" flash controller used
on the NXP KL2X and KW4xZ SoCs.

Fixes: #5788

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-01-29 16:34:49 -06:00
Kumar Gala
a394693d2f drivers: flash: NXP k6x/kw2xd: Convert to use device tree
Convert NXP k6x and kw2xd flash driver to use device tree to get the
flash controller name from device tree.  We introduce yaml bindings for
the "nxp,kinetis-ftfe" and "nxp,kinetis-ftfl" devices.

Fixes: #5788

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-01-29 16:34:49 -06:00
Anas Nashif
b8ea7c889d x86: remove HAS_DTS checking
All X86 boards are now DTS enabled.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-01-29 10:38:32 -06:00
Michał Kruszewski
aee2ff526d ext: nordic: Replace HAL and MDK with the ones from nrfx
The old HAL and MDK have been removed from the source tree.
Since RADIO HAL is not yet present in nrfx, the "nrf_radio.h" file
was temporarily moved to "nrfx/hal" folder. It will be replaced with
the proper file from nrfx in its next update.

Signed-off-by: Michał Kruszewski <michal.kruszewski@nordicsemi.no>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2018-01-29 03:02:06 +05:30