Initialize threadptr with 0 during the boot before it possibly be used
since the architectural reset state is undefined.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This make MCUboot build as Zephyr application.
Providing optinal 2nd stage bootloader to the
IDF bootloader, which is used by default.
This provides more flexibility when building
and loading multiple images and aims to
brings better DX to users by using the sysbuild.
MCUboot and applications has now separate
linker scripts.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
This patch modifies intel_adsp_ipc_is_complete function so it don't
report that IPC is completed when we are still waiting for ACK from
HOST.
This change will allow to solve the problem that occurs during the power
state transitions. Occasionally, the Application decides to enter the
power gating state after sending an IPC message, before receiving an ACK
from the HOST. This results in broken IPC communication when coming back
to Idle state.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Thanks to PR [1] which introduces support for cache management
operations on xtensa architecture NXP SoCs can now use the
Zephyr native cache management API.
This commit enables some configurations that will allow us
to use the native Zephyr cache management API.
[1]: https://github.com/zephyrproject-rtos/zephyr/pull/50136
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
The end of the heap should be the same as _heap_sentry. The current end
marker just covers the range of memory that is explicitly put in
.heap_memand not account until the end of L2_SRAM_BASE +
L2_SRAM_SIZE memory.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The macro HW_STATE_CHECK_DELAY represents the number of usec to
busy-wait when waiting for a h/w register state change. This value
has been lowered by 75% to correct a couple of issues related
to Power Management (PM).
1. This resolves a kernel.timer.tickless test failure (see
tests/kernel/timer/timer_api) on the LNL simulator where the test
was taking too long to wake after sleeping for 50 ticks. This
was tracked down to the xtensa SOC power management code where
it was performing a busy wait of 256 usec, which was equivalent
to 2.56 ticks.
2. Furthermore, this delay of 256 usec contradicted the information
in the DTSI (see power-states for d0i3) which states that the
"exit-latency-us" is 100 usec. Reducing this value to 64 helps to
keep that in line.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
This aligns `soc/xtensa/nxp_adsp/` with commit
fad2da39aa ("intel_adsp: move `west sign` from `west flash` to earlier
`west build`")
The --if-tool-available option preserves backwards-compatibility:
nothing happens if rimage is not found.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Update the SOC_TOOLCHAIN_NAME to intel_ace15_mtpm so that
we use the correct overlay in Xtensa HAL module. Note that
ace20_lnl will also be using this as well. That will change
once we have a proper toolchain for ace20_lnl.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The ACE 2.0 LNL platform has 5 HIFI4 cores. Change number
of cores to enable 5th core on the platform.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
(resubmitting after it has been reverted by 0f2a352cbd ('Revert
"xtensa: remove ELF section address rewriting"')
Now rimage can handle both cached and uncached addresses correctly,
ELF rewriting isn't needed any more.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Enable UART on the DSP from the i.MX8MP target:
- add corresponding nodes in dtsi and dts;
- create a dts overlay for uart;
- add a config fragment for uart and console configuration.
So, in order to compile an application and enable UART
a user must run west build using DTC_OVERLAY_FILE and CONF_FILE.
Here's an example for hello_world:
west build -p always -b nxp_adsp_imx8m samples/hello_world/
-DDTC_OVERLAY_FILE="boards/xtensa/nxp_adsp_imx8m/
nxp_adsp_imx8m_uart.overlay" -DCONF_FILE="boards/xtensa/nxp_adsp_imx8m/
nxp_adsp_imx8m_uart.conf"
For other applications, like SOF, where we don't need UART, we simply run:
west build -p always -b nxp_adsp_imx8m ../modules/audio/sof/ --
-DTOOLCHAIN=/opt/zephyr-sdk-0.15.2/xtensa-nxp_imx8m_adsp_zephyr-elf/
bin/xtensa-nxp_imx8m_adsp_zephyr-elf -DINIT_CONFIG=imx8m_defconfig
The nxp_adsp_imx8m is using the nxp_imx_iuart driver.
For now, is used in poll mode.
Next step is to enable the interrupt controller in
DSP and use the interrupt driver UART.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Rename soc to mimx8ml8 to link this board to the
MIMX8ML8 device from nxp_hal/mcux/mcux-sdk/.
We need this in order to use the drivers from mcux-sdk.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Do not use XTENSA_HAL when building with xt-clang, instead use the HAL
that is provided by the toolchain, similarly to xt-xcc.
Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
This patch moves cache flush/invalidation to section executed only when
IMR context saving is enabled. If this option is disabled no FW context
is stored so any lost data doesn't matter.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Masking out all interrupt during power state transition and restoring
them after is now common thing for all power states. No need to
duplicate code.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Reusing primary core context save/restore flow for purpose of secondary
core D0 -> D3 -> D0 transitions. If core is re-enabled we use
dsp_restore_vector as the FW entry point.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch is preparing cpu context save and restore code so it can be
later used by the multiple cores.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch replace temporary stack of the restore vector with interrupt
stack to reduce memory usage. Additionally we can assign seprate stack
for each core. This will allow to reuse this vector for secondary cores.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Build of Intel cAVS2.5 platforms fails due to undefined reference
sys_cache_data_flush_and_invd_all(). Fix this by adding missing
header include to bring in the inline definition for this function.
Fixes: 6388f5f106 ("xtensa: use sys_cache API instead of custom interfaces")
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Move additional cache code related to architecture support into arch.h
and leave cache.h with cache API implementation.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
To enable IMR on LNL platform new header added to
support context save/restore must be added also to LNL.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
This adds some structs for interrupt stack frames to make it
easier to access individual elements, and ultimately getting
rid of magic array element numbers in the code. Hopefully,
this would aid in debugging where you can view the whole
struct in debugger.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Introduce config for all ESP32 chips which
may be using different architectures but
shares common peripherals and features.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
The power off sequence in cavs is meant to be used only by custom pm
policy handler thus guard it with proper ifdefs.
Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
Many areas of Zephyr divide and round up without using the DIV_ROUND_UP
macro. Make use of it, so that we make use of a tested system macro and
at the same time we make code more readable.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The init infrastructure, found in `init.h`, is currently used by:
- `SYS_INIT`: to call functions before `main`
- `DEVICE_*`: to initialize devices
They are all sorted according to an initialization level + a priority.
`SYS_INIT` calls are really orthogonal to devices, however, the required
function signature requires a `const struct device *dev` as a first
argument. The only reason for that is because the same init machinery is
used by devices, so we have something like:
```c
struct init_entry {
int (*init)(const struct device *dev);
/* only set by DEVICE_*, otherwise NULL */
const struct device *dev;
}
```
As a result, we end up with such weird/ugly pattern:
```c
static int my_init(const struct device *dev)
{
/* always NULL! add ARG_UNUSED to avoid compiler warning */
ARG_UNUSED(dev);
...
}
```
This is really a result of poor internals isolation. This patch proposes
a to make init entries more flexible so that they can accept sytem
initialization calls like this:
```c
static int my_init(void)
{
...
}
```
This is achieved using a union:
```c
union init_function {
/* for SYS_INIT, used when init_entry.dev == NULL */
int (*sys)(void);
/* for DEVICE*, used when init_entry.dev != NULL */
int (*dev)(const struct device *dev);
};
struct init_entry {
/* stores init function (either for SYS_INIT or DEVICE*)
union init_function init_fn;
/* stores device pointer for DEVICE*, NULL for SYS_INIT. Allows
* to know which union entry to call.
*/
const struct device *dev;
}
```
This solution **does not increase ROM usage**, and allows to offer clean
public APIs for both SYS_INIT and DEVICE*. Note that however, init
machinery keeps a coupling with devices.
**NOTE**: This is a breaking change! All `SYS_INIT` functions will need
to be converted to the new signature. See the script offered in the
following commit.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
init: convert SYS_INIT functions to the new signature
Conversion scripted using scripts/utils/migrate_sys_init.py.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
manifest: update projects for SYS_INIT changes
Update modules with updated SYS_INIT calls:
- hal_ti
- lvgl
- sof
- TraceRecorderSource
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
tests: devicetree: devices: adjust test
Adjust test according to the recently introduced SYS_INIT
infrastructure.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
tests: kernel: threads: adjust SYS_INIT call
Adjust to the new signature: int (*init_fn)(void);
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Invoking `west sign` in `west build` accelerates twister because `west
build` is run in parallel, see rationale in superseded and very
different (CMake-based) PR #52942.
To maximize backwards compatibility:
- `west sign` is optional in `west build`
- `west flash` will sign (again) if any rimage --option is passed
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
LNL uses MM_DRV_INTEL_ADSP_MTL_TLB to save / restore context.
This is exactly the same like on MTL. Enable PM for ACE 2.0 then.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
LNL platform is ACE 2.0 series with changes in shim registers and HW
features. Initial definition replicates MTL as much as possible, however
it will vary after enabling LNL platform.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Added a new watchdog driver which can handle a multiple wdt_dw instances
and can control the pause signal.
The mlt platform has three designware watchdogs, one for each core.
I decided to create a separate intel watchdog driver for the following
reasons:
1. All three devices share the same interrupt number. Each watchdog reports
an interrupt to the core to which it has been assigned. The same interrupt
number cannot be used by multiple devices in the device tree. So, it would
be assigned to only one device. The other dw watchdog devices would use
this assignment, even though it would not be described for them in the dt.
The interrupt handler function in dw watchdog checks the interrupt flag.
If the interrupt was connected to the first watchdog, and the second or
third watchdog signal an interrupt, the interrupt handler of the first
device would ignore it because it would not have set the interrupt flag.
The watchdog device don't knows anything about the existence of the others
devices.
2. The designware watchdog only supports a hardware pause signal. It cannot
be paused programmatically. On the mtl platform, there is a separate group
of control registers for all per-core watchdogs. There are GPIO-like
registers that allows control of a hardware pause signal for subordinate
watchdogs. This separate block is shared by all three watchdogs.
3. The base addresses of the subordinate watchdogs are read from the
aforementioned control registers. As a result, in the device tree we have
only one base address for the intel watchdog, which points to the pause
control registers and containing the base addresses of the subordinate
devices.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
