The second argument 'uint32_t *hpsram_pg_mask' must be a cached
pointer and this needs to be reflected in function prototype.
Fixes sparse warning:
/zep_workspace/zephyr/soc/xtensa/intel_adsp/cavs/power.c:106:63:
warning: incorrect type in argument 2 (different address spaces)
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Converting between cached and uncached aliases should have correct
sparse annotations. Fix following sparse warning:
/zep_workspace/zephyr/soc/xtensa/intel_adsp/cavs/power.c:97:53: warning:
incorrect type in argument 1 (different address spaces)
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Use WAIT_FOR to wait for core power changes to be reflected
in status registers. If core power state does not complete in
10ms, k_panic() is raised.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Use WAIT_FOR to wait for clock source to be enabled. If clock does
not come up in 10ms, raise k_panic().
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
This adds SoC and board configs to support the dc233c core
that is available on QEMU. This core has more features than
sample_controller, such as MMU support.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
With gcc from the zephyr sdk and -Wold-style-declaration is giving this
output:
zephyr/arch/arm/core/aarch32/cortex_a_r/fault.c:101:1: warning:
'inline' is not at beginning of declaration [-Wold-style-declaration]
101 | static void ALWAYS_INLINE
z_arm_fpu_caller_save(struct __fpu_sf *fpu)
| ^~~~~~
I searched to all of the source code to find these further occurances
where inline is not at the beginning of a function declaration.
Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
The existing heap starts at the beginning of SPIRAM which is also occupied
by the WiFi stack if CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM is enabled. This
results in memory corruption.
Update the linker description to add a _spiram_heap_start symbol and add a
KConfig size option to allow the SPIRAM stack to be correctly located and
sized. Requires matching commit in hal_espressif.
Fixes: 61359
Signed-off-by: Eric Holmberg <eric.holmberg@northriversystems.co.nz>
For some weird reasons, if the sections in linker script are not
in memory address order, there are lots of padding involved in
zephyr_pre0.elf. This moves the .intList section to its memory
ordered location. When building hello_world, this shrinks
zephyr_pre0.elf from 512MB to 339KB.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Implement the sys_poweroff hook for all ESP32 SoCs based on the previous
SOFT_OFF implementation.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
In case of HDA Link DMA FIFORDY bit is RO according
to HW specification thus should be managed by HDA controller.
Add a logic to set FIFORDY for HDA Host DMA only
Signed-off-by: Ievgen Ganakov <ievgen.ganakov@intel.com>
File was using stdint.h defined types without including and caused a
build error depending on include ordering.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Add an option to control whether or not hpsram banks should
be switched off during the power down. This is particular useful
when running tests because we don't want to lose the contents
of the memory window before we capture it.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Refactor the ESP32 target SOCs together with
all related boards. Most braking changes includes:
- changing the CONFIG_SOC_ESP32* to refer to
the actual soc line (esp32,esp32s2,esp32s3,esp32c3)
- replacing CONFIG_SOC with the CONFIG_SOC_SERIES
- creating CONFIG_SOC_FAMILY_ESP32 to embrace all
the ESP32 across all used architectures
- introducing CONFIG_SOC_PART_NUMBER_* to
provide a SOC model config
- introducing the 'common' folder to hide all
commonly used configs and files.
- updating west.yml to reflect previous changes in hal
Signed-off-by: Marek Matej <marek.matej@espressif.com>
The PM hooks were guarded with CONFIG_PM_POLICY_CUSTOM, however, they
need to be guarded (if file is always compiled) with CONFIG_PM. In fact,
CONFIG_PM_POLICY_CUSTOM requires to implement a custom policy hook,
something this module did not provide.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Remove unnecessary __weak attribute from power management functions.
These functions are now defined once, globally, and mandatory for
systems that support CONFIG_PM.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add a new Kconfig option that has to be selected by SoCs providing PM
hooks. This option will be now required to enable CONFIG_PM. Before this
change, CONFIG_PM could always be enabled, regardless of SoC providing
any kind of low-power support.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The clock rates for ACE series of Intel Audio DSP have changed.
The values come from the SOF project in their board configs.
CONFIG_XTENSA_CCOUNT_HZ is also set so the arch timing test
can pass.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Align `soc/nxp_adsp` with new `WEST_SIGN_OPTS` option added to
`soc/intel_adsp` by recent commit d98a7c2f8d ("soc: xtensa: cmake: add
new WEST_SIGN_OPTS variable").
This allows per-board rimage customization at the CMake level. Example
in `zephyr/boards/xtensa/nxp_adsp_NEWBOARD/board.cmake`:
set(WEST_SIGN_OPTS -- -c rimage/config/special.toml)
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Instead of relying on direct memory access via structs to
control CPU power and status, using inline functions instead
to hide the details. This makes reading the common code a bit
cleaner.
The function names are generic and not architecture or
platform specific, in an attempt to ease future arch or
platform additions with code reuse. Or else we would need to
rename these.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Some boards has ESP_SPIRAM enabled by default, which is
causing issues when MCUboot is used as 2nd bootloader.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
This fixes the following build error:
```
zephyr/zephyr.elf', needed by 'zephyr/zephyr.ri', missing and no known
rule to make it
```
This appears when CONFIG_KERNEL_BIN_NAME is used.
Therefore, do not use zephyr.elf since some samples might be called
based on CONFIG_KERNEL_BIN_NAME.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
The Zephyr linker scripts have inconsistent ordering of various chunks of
data which lands in RAM at runtime. This leads to the value of _end not
being consistently defined as the maximum address of static variables used
in the application.
Create a helper linker fragment, zephyr/linker/ram-end.ld, which can be
included after the last possible definition of RAM data, that consistently
sets _image_ram_end, _end and z_mapped_end.
Signed-off-by: Keith Packard <keithp@keithp.com>
After exiting D3 state if IMR context save is enabled, IDC interrupt
must be re-enabled again for all cores.
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
The ifdefs in in dmic headers is getting out of control and makes
maintainence very ddifficult, especially when having to maintain out of
tree SoCs sharing the same data and information.
Keep header clean and per SoC and share some common registers in one
place instead avoiding confusion and making it easier to read and
maintain.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
When CONFIG_PM_DEVICE is enabled IPC Device may be during power transition
during a call to intel_adsp_ipc_send_message function.
Changed signatures of intel_adsp_ipc_send_message and its sync version
to return int and negative error codes on error.
On attempt to send IPC message during Device power transition
-ESHUTDOWN error code is returned, on busy state -EBUSY.
Updated all function references.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
When option CONFIG_PM_DEVICE is enabled, IPC driver is capable
of entering D3 power state described as PM_DEVICE_ACTION_SUSPEND
(and leaving that state - powering back to PM_DEVICE_ACTION_ACTIVE).
New power control callbacks 'ipc_power_control_api' are introduced for
use during power state transisions. They allow Zephyr application
specific code to be executed.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
Exiting idle state requires to reinitialize all memory window
instances to flush the cached memory.
Added function that calls initialization of devices during runtime.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
Generic header for system clock allows to define a sys_clock_idle_exit
function for the clock implementation.
Implemented the function in the intel_adsp_timer to reinitialize
device driver after the idle exit state.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
Provides a way to use pinctrl to allow internal loopback
on a peripheral pin for testing purposes.
This is done by using output-enable on a input pin and
input-enable on a output pin.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Added a new function to check whether a clock source is supported by a
platform and to retrieve its frequency.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
The word cpu was added to the names of functions, structs, types
and definitions to disambiguate the names and make room in the namespace
for soc clock control functions.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Add simple mechanism to load the image from IMR memory. Basically we are
only setting a flag in power off for the next boot to jump to existing
image in IMR.
Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
Amount of memory banks should vary depending on platform, otherwise
power down sequence might result in ipc timeout as the memory used by
the ipc itself is shutdown.
Lift the needed defines from sram.c to adsp_memory.h and shorten the
names to avoid collision with sof code. No functional change to sram.c.
Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
It doesn't make sense to select this option at SoC level. This feature
is meant for subsystems/modules that need device handles to be
modifiable at runtime.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The field offset is incorrect, L1EXP is at bit 24 and L1ETP at bit 25.
Fixes: cc6e9c094a ("soc/intel_adsp: Low level HDA driver and tests")
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Updated the flash segment alignment on S3,
so that mapping corresponds with the linkage.
Fixed hard-coded flash size for ESP32.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
For Intel cavs2.5, access from LPGPDMAC to Audio Link Hub
RX/TX registers needs to be explicitly enabled before use.
The logic follow hardware initialization done in
SOF project sof/src/platform/intel/cavs/platform.c
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The SoCs/Boards using those headers were dropped, so remove those
remaining headers that were forgotten.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
