soc: riscv: andes_v5: include soc_v5.h

Instead of catch-all soc.h (which was now just being a proxy for
soc_v5.h).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>

soc/riscv/andes_v5/ae350/l2_cache.c

@@ -10,6 +10,8 @@
  * @brief Andes V5 L2 Cache Controller driver
  */
 
+#include "soc_v5.h"
+
 #include <zephyr/init.h>
 #include <zephyr/kernel.h>
 #include <zephyr/arch/cpu.h>

soc/riscv/andes_v5/ae350/soc.h

@@ -11,7 +11,4 @@
 #ifndef __RISCV_ANDES_AE350_SOC_H_
 #define __RISCV_ANDES_AE350_SOC_H_
 
-/* Include CSRs available for Andes V5 SoCs */
-#include "soc_v5.h"
-
 #endif /* __RISCV_ANDES_AE350_SOC_H_ */

soc/riscv/andes_v5/ae350/soc_irq.S

@@ -4,11 +4,11 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include "soc_v5.h"
+
 #include <offsets.h>
 #include <zephyr/toolchain.h>
 
-#include <soc.h>
-
 #ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
 
 /* Exports */

soc/riscv/andes_v5/ae350/start.S

@@ -4,8 +4,9 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include "soc_v5.h"
+
 #include <zephyr/toolchain.h>
-#include <soc.h>
 
 /* exports */
 GTEXT(entry)