Added initial version of Infineon CAT1 UART driver.
Added initial version of binding file for Infineon CAT1 UART driver.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Add initial version of Infineon CAT1 clock control driver.
- supports clock initialization based on board DT configuration.
Added initial version of system_clocks.dtsi for Infineon PSoC 6 SOC.
Includes: clk_imo, path_mux0..4, fll0, pll0, clk_hf0..4, clk_fast,
clk_slow and clk_peri.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Added initial version of Infineon CAT1 Pin controller driver.
Added initial version of binding file for Infineon CAT1 Pinctrl driver.
Added initial version of dt header for Infineon CAT1 pinctrl driver.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Added initial version of Devicetree for Infineon PSoC 6 SOC with following
structure:
1. MPN devicetree files
|--> psoc6
|--> mpns
|--> CY8C6016BZI_F04.dtsi
|--> CY8C6036BZI_F04.dtsi
|--> CY****.dtsi
Those file describes cpus, flash-controller, sram memory, nvic option. It
includes the package dtsi (e.g. psoc6_02.124-bga.dtsi) with information
about gpio (based on package e.g. 68-qfn, 128-tqfp, 124-bga, etc.) and
peripherals for (based on PSoC 6 series, psoc6_01, psoc6_02, etc).
MPN devicetree file is main platform dtsi file, which should be included
from board dts (e.g cy8cproto_062_4343w.dts), example:
#include <infineon/psoc6/mpns/CY8C624ABZI_S2D44.dtsi>
2. Devicetree files for PSoC 6 series 02 (2M).
Includes: psoc6_02.dtsi - peripherals dtsi psoc6_01.xxxxx.dtsi - package
dtsi. User does not directly include those files.
It automatically includes via MPN dtsi.
|--> psoc6_02
|--> psoc6_02.dtsi
|--> psoc6_02.100-wlcsp.dtsi
|--> psoc6_02.124-bga.dtsi
|--> psoc6_02.128-tqfp.dtsi
|--> psoc6_02.68-qfn.dtsi
In future PR/commits will be added Devicetree for support all
PSoC 6 series:
- for PSoC 6 series 01 (1M)
- for PSoC 6 series 03 (512)
- for PSoC 6 series 04 (256)
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Provide dts binding for F412 PLL I2S.
This I2S dedicated PLL is fully configurable and take same
input as Main PLL
Only one output clock (PLLR) is supported for now.
This PLL could be found on STM32F412 and F413 parts for instance.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Provide dts binding for F4 PLL I2S.
This PLL share input source and input M diviso with F4 Main PLL.
Only one output clock (PLLR) is supported for now.
This PLL could be found on STM32F401 parts for instance.
Additionally, provide related header definitions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Polarity support added to XEC PWM driver. This allows (for example) PWM
controlled LEDs that are active low to actually be turned off when set
to off.
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Rework the Host Command support. It includes:
-change API to backend
-change a way of defining rx and tx buffers
-fix synchronization between the handler and backend layer
-simplify the HC handler
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Follow naming pattern in the subsystems(logging or shell) and name
the layer between generic handler and peripheral driver "backend".
The name doesn't suit that well to the SHI backend, because there isn't
SHI API itself and the SHI interface is used only for the host
communication. So the backend code includes the peripheral driver itself.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Change the dtsi order for the stm32L4plus serie,
starting with stm32l4p5-stm32l4q5 and stm32l4r5-stm32l4s5
Significant changes are on the SRAM size, the sdmmc2
and separated RTC-bbram registers.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The SRAM1(total 192 KBytes) plus SRAM2: (total 64 KBytes)
plus SRAM3(total 512 KBytes) is available from 0x20000000 to
0x200BFFFF.
The SRAM size is only 768KB at address 0x20000000
The 16KB SRAM4 is located at address 0x28000000 so that no ram
is present from 0x200c0000 to 0x28000000.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the implementation for the akm09918c magnetometer driver.
Additionally, add the appropriate node to the TDK robokit1 device
tree. In order to prevent regressions, add the sensor to the sensor
build_all tests and specific tests using an emulator.
Signed-off-by: Yuval Peress <peress@google.com>
Add a driver implementation that uses the I2S peripheral.
Based off this blog post:
https://electronut.in/nrf52-i2s-ws2812/
Should help with #33505, #29877 and maybe #47780, as there is no garbage
data at the end of transmissions on nRF52832, and no gaps.
Signed-off-by: Jonathan Rico <jonathan@rico.live>
Some register addresses change within the AM6X family.
AM62X is common to AM623X/AM625X processors.
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
STM32L4plus mcu has SDMMC internal DMA which works without any
configuration and it's handled by SDMMC HAL driver. This commit adds
option to enable it and use it.
Signed-off-by: Petr Hlineny <development@hlineny.cz>
For STM32L47x and STM32L48x, the high calibration value for temperature is
110. For all other STM32L4xx, it is 130. So we set 130 by default and set
it to 110 for L471.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
ADC3 is already defined for STM32L471 which is included in STM32L476 and in
STM32L496 so no need to define it a second time.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
