1. adjusted enet_qos driver to cope with features missing on mcxa577
2. enabled enet_qos support
3. verified samples/net/zperf
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
ltdc controller is also available in stm32l4r5 and stm32l4q5
so add it within stm32l4p5. It is not available in stm32l4r5
hence delete the node for this platform.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
As done with ST MCU boards, enable all gpios at SoC level to avoid
to handle them at board level.
Signed-off-by: Christophe Guibout <christophe.guibout@st.com>
Add the stm32mp21x initial device tree source based on stm32mp2_m33.dtsi
stm32mp21 series boards, covering non-secure configuration for zephyr on
the Cortex-M33 core.
These files provide the basic hardware description, including CPU
(Cortex-M33), memory, and RCC clock controller.
Also factorize stm32mp2_m33.dtsi where some definitions were only dedicated
to stm32mp25x, split IRQ number declaration which are different
between stm32mp25x and stm32mp21x.
Signed-off-by: Christophe Guibout <christophe.guibout@st.com>
Add devicetree nodes for the UDP peripheral on SAM4S and SAM4E SoCs,
along with the corresponding devicetree binding.
The UDP controller is present at:
- SAM4S: 0x40034000, IRQ 34
- SAM4E: 0x40084000, IRQ 35
Both variants share the same compatible "atmel,sam-udp" and feature:
- 8 hardware endpoints (EP0-EP7)
- 1 bidirectional endpoint (EP0 for control)
- 5 IN endpoints, 4 OUT endpoints
- Full-speed USB 2.0 (12 Mbps)
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The bits cell for KINETIS_SIM_DMA_CLK and KINETIS_SIM_DMAMUX_CLK was
incorrectly set to 0x00000002 (a bitmask), but the driver passes this
value directly as the bit-shift index to CLK_GATE_DEFINE(). The HAL
defines:
kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 1U)
kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U)
Fix the bit index to 1 in both nxp_k6x.dtsi and nxp_k8x.dtsi.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Update the clock-cells documentation to describe the 32-bit `name` (id)
cell encoding produced by KINETIS_SIM_CLOCK(). The explicit offset and
bits cells are retained with a note that they exist for consumers such as
the ADC16 driver that read them directly rather than via clock_control.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Replace all raw 3-cell clock specifiers in nxp_mcxc_common.dtsi with
KINETIS_SIM_CLOCK() macro calls. CMP and VREF legacy alias specifiers
are replaced with their real SCGC4 gate addresses (bits 19 and 20);
DMA and DMAMUX are replaced with their SCGC7/SCGC6 gate addresses.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Replace all raw 3-cell <&sim KINETIS_SIM_FOO 0xOFFSET BIT> specifiers
with the new KINETIS_SIM_CLOCK() macro. The macro encodes gate offset,
gate bit, and clock name into the first (id) cell while keeping the
explicit offset/bits as the 2nd and 3rd cells for ADC16 and other
consumers that read them directly.
ENET and ENET_1588 legacy alias specifiers (which used invalid out-of-range
clock-name values) are replaced with their real SCGC2 gate register
addresses (offset 0x1028, bit 26).
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Split interrupt configuration from am64x_r5.dtsi into individual
R5F core files (am64x_r5f0_0.dtsi, am64x_r5f0_1.dtsi,
am64x_r5f1_0.dtsi, am64x_r5f1_1.dtsi) as each core uses
different mailbox channels and VIM interrupt line mappings.
Signed-off-by: Dave Joseph <d-joseph@ti.com>
Add interrupt-names property to binding to enable per-channel
interrupt lookup via DT_INST_IRQ_BY_NAME(). Each channel's
interrupt is identified by name: "rx_0", "rx_1", "rx_2", etc.
Signed-off-by: Dave Joseph <d-joseph@ti.com>
This adds initial support for the CH32V ethernet peripheral.
The driver supports both internal and external PHY configurations.
Signed-off-by: James Bennion-Pedley <james@bojit.org>
Use PSCI CPU suspend to implement CPU idle for Cortex-A55 Core on i.MX 93.
Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
For use in tests where the existing "vnd,dac" driver doesn't work as it
returns error codes for all API functions. The approach is mimicked from
the adc-emul driver.
Signed-off-by: Henrik Lindblom <henrik.lindblom@vaisala.com>
Instead of using MCOX specific check with STM32MP1 devices,
the dedicated enable bit is defined in device tree.
This breaks compatibility with old DT overlays for
STM32MP13 devices.
The new overlay should now have 2 clocks, where the 1st one
is the enable bit, e.g. like:
clocks = <&rcc MCO1CFGR_REG BIT(12)>, <&rcc ...>;
Signed-off-by: Adam BERLINGER <adam.berlinger@st.com>
The change introduces clock-names into the MCO device tree.
This shouldn't break compatibility with existing DT overlays.
It clarifies the clock configuration for devices
with dedicated enable bit for MCO.
Signed-off-by: Adam BERLINGER <adam.berlinger@st.com>
Adapt all Espressif SoC and driver code to the updated
hal_espressif module synced with IDF master branch.
Main changes:
- clock control: delegate peripheral clock gating to HAL
layer using new clock/reset APIs
- SPI/GDMA: adapt to restructured DMA HAL with new channel
allocation and configuration interfaces
- ethernet: add RMII clock configuration and PHY management
- GPIO: simplify using direct HAL function calls
- flash: adapt to updated SPI flash HAL interfaces
- linker scripts: update IRAM/DRAM mappings for new HAL
object files
- DTS: fix ESP32-S2 PSRAM dcache1 address to match actual
MMU mapping region (0x3f800000 DRAM1 instead of 0x3f500000
DPORT which lacks 8-bit access capability)
- west.yml: update hal_espressif revision
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add Atmel SAM USBHS driver for SAM E70/S70/V70/V71 family. The driver
was tested using CDC-ACM and testusb samples.
Fixes: #74663
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Rename microchip,aes-g1 binding file to match compatible, fixes a:
dts/bindings/crypto/microchip,aes-g1-crypto.yaml: bad file name for
compatible 'microchip,aes-g1'; this should be named
'microchip,aes-g1.yaml' instead
error on unrelated PRs.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The simulated flash driver incorrectly applied the no_explicit_erase
capability. It was overriding Kconfig settings with a missing Devicetree
property, which caused RAM-like configurations to wrongly report needing
explicit erases before writes.
This commit fixes the initialization macro to correctly check the DT
instance property no-explicit-erase, while properly falling back to the
global CONFIG_FLASH_SIMULATOR_EXPLICIT_ERASE Kconfig.
A new runtime test is also added to properly verify this capability.
Fixes#100352Fixes#100400
Signed-off-by: Seyoung Jeong <seyoungjeong@gmail.com>
We update MEC172x and MEC174x/5x/165x device tree I2C hardware
nodes with properties used by the updated I2C V2 driver. GIRQs
are an array of integers where each integer encodes the GIRQ
number and bit position of each interrupt source. The PCR property
is a single integer encoding the PCR register index and bit position.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
We modified the Microchip XEC/MEC version 2 I2C byte mode driver
to work on v3.8 I2C hardware in MEC174x/5x/165x SoCs. The changes
are as follows:
1. Add a local header file containing register and bit field definitions
2. Use Zephyr inline register access functions (sys_read/write)
instead of CMSIS register structures.
3. Change DT bindings to require GPIO references for the SCL and SDA
pins. MEC172x will use GPIO driver to get line states. MEC174x/5x
have v3.8 I2C hardware with read-only live values of SCL/SDA pin
states in the bit-bang control register. The MEC172x SoC code to
read I2C GPIO's is no longer needed and is removed in a later
commit in this series.
4. Use WAIT_FOR macro in place of custom spin loops.
5. SonarQube code check recommendations except WAIT_FOR macro which is
based on a GNU compiler extension.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Allow providing an unlock configuration for unlocking the padcfg region as
part of the ti,control-module node.
Map the child pinctrl node using the `ranges` property to the base address
space.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
Allow providing an unlock configuration for unlocking the padcfg region as
part of the ti,control-module node.
Map the child pinctrl node using the `ranges` property to the base address
space.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
This binding is for TI devices that use control modules for configuring
registers and information related to control MMRs, power, reset and
clocking.
These control modules consist of regions that require writing specific
values to specific kick registers to unlock that region. This is provided
as ti,unlock-offsets property.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
This 'base' file is just an include file, it doesn't actually refer to
a concrete binding. There's a specific binding for the 4050 in another
file that has the right name.
Signed-off-by: Martí Bolívar <marti.bolivar@oss.qualcomm.com>
We have:
- sifive-common.yaml that wants to be a generic include
file for CPUs by that vendor
- riscv.yaml that is *both* a generic include file for CPUs of that
architecture *and* a specific binding with compatible "riscv"
This is a problem for multiple reasons:
1. It means that both sifive-common.yaml and riscv.yaml are different
YAML files with the same "compatible", i.e. "riscv".
This should be a hard error. The only reason this isn't causing build
errors seems to be because of an edtlib optimization (see the
"dt_compats_search" in edtlib.py for details)
2. It means that sifive-common.yaml is a valid binding whose file
name doesn't match its compatible, which is a violation of the
rules for upstream bindings.
Fix both of these problems by factoring out the common properties into
a new "riscv-common.yaml" that doesn't have any "compatible: " set.
That lets sifive-common.yaml just include riscv-common.yaml, allowing
it to be "just" an include file, without breaking any of the common
property definitions expected by CPU bindings for that vendor.
Note that there does appear to be one file
in-tree (dts/riscv/raspberrypi/hazard3.dtsi) that actually uses
"riscv" as a bare compatible. I'm going to take that as a hint that
out-of-tree users are probably doing the same, making it important to
continue to allow riscv.yaml to be a "real" binding and not "just" an
include file.
Signed-off-by: Martí Bolívar <marti.bolivar@oss.qualcomm.com>
The main problem I want to fix here is that the DT binding's file name
doesn't match its compatible, which is a violation of our upstream
bindings rules.
The "dsi" suffix here is not a good practice, DT-wise. The compatible
string represents the programming model for the device in vnd,device
format. We don't put the "-spi" at the end of compatibles for SPI
devices, and we don't put "-pcie" on the compatibles for PCIe devices.
The bus has no place in the DT compatible. So in this case, the
file name seems fine, but the compatible itself is off.
(The other option would have been to change the suffix to "mipi-dsi"
(or "mipi_dsi") as necessary to match the relevant "on-bus:" value in
the binding -- but let's simplify and better align with DT best
practices here.)
Signed-off-by: Martí Bolívar <marti.bolivar@oss.qualcomm.com>
A YAML file with a "compatible:" set is able to be interpreted by the
bindings system as a "real" binding and should have enough information
to feed a driver. YAML files without "compatible:" are meant to be
used with the "include:" feature.
Delete some stray "compatible:" lines that are in YAML files seemingly
meant only to be used as include files.
Signed-off-by: Martí Bolívar <marti.bolivar@oss.qualcomm.com>
These bindings' filenames don't match their compatibles, but the fixes
weren't automated as there were multiple possible outcomes for these.
I looked around and fixed them up by hand.
Signed-off-by: Martí Bolívar <marti.bolivar@oss.qualcomm.com>
Clean up various bindings whose names do not match our naming policy.
These are all unambiguous cases I found and fixed with a quick script.
As a reminder, the policy in bindings-upstream.rst is:
Bindings which match a compatible must have file names based on
the compatible.
- For example, a binding for compatible ``vnd,foo`` must be named
``vnd,foo.yaml``.
- If the binding is bus-specific, you can append the bus to the
file name; for example, if the binding YAML has ``on-bus: bar``,
you may name the file ``vnd,foo-bar.yaml``.
Signed-off-by: Martí Bolívar <marti.bolivar@oss.qualcomm.com>
Add device tree include file for the Alif Ensemble E1C SoC
variant AE1C1F4051920PH0.
The file builds upon the common peripheral definitions from
ensemble_common.dtsi and ensemble_rtss_he.dtsi and defines the
SoC specific clock frequencies, TCM configurations and MRAM
configuration.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Add support for hardware-generated periodic compare events using
the GRTC interval feature. Once configured, the hardware generates
compare events at a fixed interval without CPU intervention.
The feature is available only on channels defined as
"extended-channels" in the devicetree.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
