Removes label and compatible properties
from the flash section. The properties are
provided by included stm32h723.dtsi.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
* Corrects SRAM0 size. The `TCM_AXI_SHARED`
is `000` after reset. That means ITCM
is shared with SRAM0.
* Adds missing SRAM1,2,4, and ITCM
regions.
* Adds label and compatible properties
to the flash section.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Enable pin control for lpc11u6x i2c driver, and remove pinmux usage from
board level DTS files.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
convert lpc11u6x syscon clock driver to pin control, and remove all
pinmux usage from driver and syscon dts node.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update pin control driver for lpc11u6x. This SOC does not have a HAL,
so fsl_clock is not available. It also lacks a slew-rate field in the
IOCON register, so this property must be optional.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
switch gpio driver to use pio nodes to configure pin control settings,
and stop using pinmux driver within gpio driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
soc: arm: privilege: add Cyclone V SoC FPGA suppport
Add support for the Intel Cyclone V SoC FPGA (arm Cortex-A9).
Signed-off-by: Esteban Valverde <esteban.valverde.vega@intel.com>
Since implementation of clock source selection in consumer device drivers
could be achieved without usage of a clock-names property and no
example of usage is provided up to now, remove this property from existing
examples.
Additionally, make it clear in stm32 clock control binding that it is
driver's responsibility to correctly access clock source information
and use it as required.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add clock sources bindings on F0/F3/G0/G4/L0/L1/L4/WB/WL series.
Due to inconsistencies, some common bindings are now split:
F1 -> F0/F1/F3
L4 -> L4/G4/WB
Update .dtsi files when required
In a first step, allowed sources are limited to already supported
clocks: LSI/LSE/HSI/HSE/MSI/PCLK/PLLCLK/SYSCLK
Support for other clocks such as HSI48, SAIXCLK, ... is left for a
next step.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This new binding allows to work on providing stm32u5 specific
alternate and complementary device clocks.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add STM32 clock mux binding.
Only property of a node using such compatible is to
select a clock input.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
e8e88dea incorrectly changed registers
used in `sys_clock_cycle_get(32|64)` functions.
This commit fixes that.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
This is a follow-up to commit 586e26e8fc.
Add missing `qdec0` node labels in definitions of SoCs that have only
one QDEC instance so that the `HAS_HW_NRF_QDEC0` option is properly set
for them. Use the same pattern as in the WDT case and keep the existing
`qdec` labels for backward compatibility.
Also update validation of base addresses so that both QDEC0/QDEC and
QDEC1 are checked.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Use the UPLLCK clock for the CAN controller as recommended by the Atmel SAM
E70 data sheet.
Move the configuration of the clock prescaler from Kconfig to devicetree
and limit it to the values recommended by the SAM E70 datasheet.
Fixes: #45012
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
In #45014 the m_can compatible identifier was changed from "m-can-base"
to "m_can-base" while #45216 was being developed. This commit updates
the dts for u5 to the latest format.
Signed-off-by: Peter Maxwell Warasila <madmaxwell@soundcomesout.com>
In order to bring consistency in-tree, migrate all dts code to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to zephyrproject-rtos#45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Cleaned up the IPC configuration for nRF5340 SoC in Device Tree. This
change fixes the (simple_bus_reg) warning about the missing or empty
reg/ranges property.
This is a follow-up to commit cf6a58d.
Signed-off-by: Kamil Piszczek <Kamil.Piszczek@nordicsemi.no>
Adds addresses and names for individual CSR registers to device tree.
This way liteuart driver no longer depends on CSR data width being 8
bits.
Also when register names or their number changes, then overlay generated
by LiteX will be incompatible with one defined here.
This should make finding breaking changes easier.
I also appended `_ADDR` suffix to defines, to distinguish them from
normal values like `LITEETH_EV_RX`.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Adds addresses and names for individual CSR registers to device tree.
This way liteuart driver no longer depends on CSR data width being 8
bits.
Also when register names or their number changes, then overlay generated
by LiteX will be incompatible with one defined here.
This should make finding breaking changes easier.
I also appended `_ADDR` suffix to defines, to distinguish them from
normal values like `UART_EX_TX`.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
