Some flash properties are currently in the individual SoC definitions,
while they are common to the whole STM32H743/753 SoC line. Move them one
level higher.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
h753
Some flash properties are currently in the individual SoC definitions,
while they are common to the whole STM32H7A3/STM32H7B3 line. Move them
one level higher.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Platforms that enable UART_NS16550_ACCESS_IOPORT (the case for ia32)
require reg-shift to be zero. Fix this issue introduced in
4c8a8149de.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The armv8 timer, arm gic, and arm gic-v3-its don't use or need the
devicetree label property. Update the dts bindings to not require it and
remove setting of the label property in dts files.
Signed-off-by: Kumar Gala <galak@kernel.org>
In 8f9290d2741844 ('dts: bindings: riscv: Add and use bindings for
sifive CPUs'), new compat strings for SiFive CPUs were added, but with
riscv prefixes. Vendor-specific compats should just be prefixed with the
vendor, so move that over here.
Fixes: 8f9290d2741844 ('dts: bindings: riscv: Add and use bindings
for sifive CPUs')
Signed-off-by: Olof Johansson <olof@lixom.net>
G4 and U5 series missed clock information in DT. Driver likely worked
because it was using HAL helpers, bypassing the purpose of DT and clock
control drivers. The clocks property is now required in the binding
file.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Adds `four-byte-opcodes` property. When set, then used write and read
opcodes will be converted to 4-Byte opcode.
Doesn't convert erase opcodes yet.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Adds write opcode (`writeoc`) property. That allows to provide
custom write opcode in the DTS.
Doesn't support OPI mode.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
The driver supported getting register shift from Devicetree, from a
custom definition in SoC headers (fragile) or, it took a default value.
This change simplifies things by making reg-shift property required in
all instances.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The ns16550 flags reg-shift property as optional. In case it is not
supplied, the ns16550 driver relies on a value defined in <soc.h>, or,
by default it takes 4 (shift by 2).
This patch adds the property to all ns16550 nodes, with the following
values:
- 2 if SoC did not have any custom value defined by
UART_REG_ADDR_INTERVAL (corresponds to 1 << 2 = 4)
- If SoC defined DEFAULT_REG_INTERVAL (snps_arc_iot/it8xxx2), use such
value (4=2, 2=1, 1=0).
These changes will allow simplifying the ns16550 driver.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
- The MX25UM51345G flash is connected to FLEXSPI PortA for
mimxrt595_evk.
- Updated flexspi_mx25um51345g driver to support DTR OPI mode.
- Tested with tests/drivers/flash.
Signed-off-by: Chay Guo <changyi.guo@nxp.com>
Enable access to the HS_SPI pins(JP26) on the mimxrt595_evk board.
Using DMA mode, tested with spi_loopback testcase.
Signed-off-by: Chay Guo <changyi.guo@nxp.com>
WWDG1 doesn't work on STM32H7 because its peripheral clock
is never enabled due to wrong enable bit in RCC_APB3ENR
Signed-off-by: Emil Lindqvist <emil@lindq.gr>
All the gpio drivers are based on devicetree and thus we always set
HAS_DTS_GPIO, thus we don't need this Kconfig option anymore. Remove
uses as its safe to assume DTS is supported for GPIO.
Signed-off-by: Kumar Gala <galak@kernel.org>
All the watchdog drivers are based on devicetree and we dont utilize
HAS_DTS_WDT anywhere so we can remove it.
Signed-off-by: Kumar Gala <galak@kernel.org>
The STM32F723 SoC has 16 kB of ITCM RAM mapped at address 0x00000000.
Tested using zephyr_code_relocate().
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The reserved memory mechanism (sections and regions definition) has been
entirely replaced, greatly extended and made it better by the work done
on the zephyr,memory-region compatible.
Since there is are no actual users, we can remove it.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This reverts commit 7f51907fda.
The problem with setting the priority at the highest priority possible
is that when the IPC is under high traffic, the WQ could starve the
scheduler.
Move back to a more sane preemptive priority as default value.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This includes DTS bindings for the Texas Instruments CC13xx/CC26xx flash
controller driver and adds support for it in CC1352R and CC2652R SoCs
DTS files.
Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
Recently OpenAMP introduced the possibility to set the sizes for TX and
RX buffers per created instance. Expose this also to Zephyr users by
using a DT property "zephyr,buffer-size".
For the sake of simplicity use the same DT property to set the buffer
size for both TX and RX buffers.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Extends #43119 with PPB and IO values of
`memory-region-mpu`.
That allows MPU region definition with
PPB or IO attributes in the DTS.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
This patch adds DTS properties for using wake-up mode
and the autosleep function to the ADXL362 driver.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
Add a pseudo device diver with device tree bindings for coredump.
The device tree bindings exposes memory address/size values to be
included in any dump. And the driver exposes an API to add/remove
dump memory regions at runtime.
Signed-off-by: Mark Holden <mholden@fb.com>
This commit aligns SPIM shim to utilize memory-region property from
nordic,nrf-uarte compatible. The memory-region is not required
property that enables user to specify placement of dma buffers
in memory region. It is done by assigning to memory-region property,
phandle to node with zephyr,memory-region and mimo-sram compatible.
When memory-region property is not specified for given
instance, buffer is placed in default RAM region with other data.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
This commit aligns UARTE shim to utilize memory-region property from
nordic,nrf-uarte compatible. The memory-region is not required
property that enables user to specify placement of dma buffers
in memory region. It is done by assigning to memory-region property,
phandle to node with zephyr,memory-region and mimo-sram compatible.
When memory-region property is not specified for given
instance, buffer is placed in default RAM region with other data.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
Since the introduction of the `zephyr,memory-region` compatible
to create new memory region, drivers can now use the newly defined
region in the DT by using the macro LINKER_DT_NODE_REGION_NAME()
on the node_id to retrieve the region name and possibly allocated data
or variables in that region (or for whatever other use).
This is assuming though that the driver knows in advance the node_id to
reference.
A better approach is to add a new generic 'memory-region' property
that can be used by any driver to reference a region by using a phandle,
so that the driver can use that to retrieve the memory-region of interest.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The ALH is an intermediary device, which acts as a hub and provides an
abstracted support for numerous sound interfaces (e.g. SoundWire).
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
To support both 8-bit and 32-bit Control/Status register variants, register
offsets need to be calculated from device tree.
Updated register data in device tree to the 32-bit CSR variant.
Renamed defines to be similar to other LiteX drivers.
Changed frequencies in clock-outputs nodes, so i2s/litex sample works.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Correct width when accessing LITEETH_RX_LENGTH register.
Also update register data in device tree to the 32-bit CSR variant.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Make driver take register info from device tree so it can work with both
8-bit and 32-bit CSRs.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Adds few missing zephyr/ prefixes to leftover #include statements that
either got added recently or were using double quote format.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This sensor is virtually identical to the lsm6dso. The only difference
is the accelerometer ranges are double those of the lsm6dso.
Use the same driver. The difference is detected by using "st,lsm6dso32"
as the first compatible entry, followed by "st,lsm6dso".
An bit flag in the existing accel_range config field is used to check if
the chip is the doubled range or not.
Signed-off-by: Trent Piepho <trent.piepho@igorinstitute.com>
Fix various board fixed-partition definitions where the devicetree cell
has been defined oddly, such as 9 nibbles (which makes no sense since
the cells are 32 bit) or 7 nibbles where all the others are 8.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Fix PM minimum residency time and exit latency for rt11xx to reflect
actual delays when entering and exiting low power modes.
Fixes#45750
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Set the priority of the wwdg instance to 6
else a build error happens :
static assertion failed: "Invalid interrupt priority.
Values must not exceed IRQ_PRIO_LOWEST"
Signed-off-by: Francois Ramu <francois.ramu@st.com>
LPC55sx6 SOC has NXP Manufacturing Programmed Area(NMPA) stored at
offsets 0x3EC00-0x3FDFF. Correct uuid offset to be within this region.
Fixes#43870
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
All the SPI1,2,3 clock of the stm32h7x mcus
are sourced by the PLL1_Q by default. This must be set
in the DTS to have a valid clock rate calculation.
The pll1_q is divided by the <div-q> property of the pll node.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
