Once the TPM driver and the required configs have been added,
now this patch enables the usage of the PWM framework on KW41Z
SoCs. As such, the DTS gets the proper nodes and the pinmuxing
is done according to the configuration requested.
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
The TPM (Timer/PWM Module) is a 2- to 8-channel timer which supports
input capture, output compare, and the generation of PWM signals to
control electric motor and power management applications.
This patch adds the driver and the binding necessary for instantiating
the driver. The work is based on the RV32M1 driver for TPM done by
Henrik Brix Andersen. A later patch will enable this driver to be used
for the KW41Z SoC, if PWM support is requested.
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
* Define USB driver for base stm32wb device.
* Enable USB for the nucleo_wb55rg board.
* Properly initialize USB power + clock for the platform.
Signed-off-by: Pete Johanson <peter@peterjohanson.com>
This patch introduces the periph to/from memory dma transfer
using the dmamux feature and define new values
for dma cells on client side
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Reworked sam_gmac driver to get pin ctrl/mux configuration information
from the device tree instead of via Kconfig and defines in soc_pinmap.h
We remove defines from soc_pinmap.h that are no longer needed due to
getting all that information from devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The Atmel SAM D5x and E5x series SoCs include the ARM memory protection
unit that supports up to 8 memory regions.
This commit adds the missing device tree MPU node to `samd5x.dtsi`,
which is used by both the SAM D5x and E5x series SoCs.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This patch is defining the DMA1 & 2 for the sm32l4 series
with 7 channels and support of mem2mem transfers
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This includes the dma cells as client for the spi
An example of the client part is defined in the dma.yaml
Consequently, bindings for the dmas property becomes then 'not required'
Including dma.yaml is not needed as dma properties
are now part of base.yaml
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add device tree nodes for the Digital-to-Analog (DAC) modules present
in the NXP Kinetis K6x series.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Add device tree node for the Digital-to-Analog (DAC32) module present
in the NXP Kinetis KE1xF series.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Add initial devicetree for the NXP LPC55S16. Only non-secure (ns)
access is supported for now.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Do not assume in the SoC level device trees that NXP Kinetis FlexTimer
nodes will always be configured as PWM. Instead, configure FlexTimer
nodes for PWM at the board level for NXP Kinetis boards.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Rework the atom/linker.ld to match how ia32/linker.ld works with regards
to how PHYS_LOAD_ADDR & PHYS_RAM_ADDR are set based on CONFIG_XIP and
from which DT_PHYS_{RAM,LOAD}_ADDR defines. We update the minnowboard
dts and atom.dtsi files to keep in sync with this.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Rework the devicetree to utilize new DT_INST macros and extract per
instance data for clocks from devicetree.
We add a property ('calib-offset') for the SAM{D,E}5x family of SoCs
that is the bit position offset from ADC0 BIASCOMP in the NVM Software
Calibration Area Mapping. For ADC0 this is typically 0 and for ADC1
this will be 14.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In STM32 can driver CAN2 instance need to know the base address
of CAN1 instance which is referenced as master can.
Add this information as an optional property to stm32 can binding.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
By defaut, only one uart is used as console.
Disable unused peripherals in dts to avoid
conflicts (issue #23475), save memory footprint,
and reduce the boot time.
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Convert driver to use the new device tree macro's instead of
dts_fixup.h based macros. This moves us closer to removing both
dts_fixup.h and per instance Kconfig symbols.
The pinmux_mchp_xec is also being updated since it's using DT
from GPIO.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Convert driver to use the new device tree macro's instead of
dts_fixup.h based macros. This moves us closer to removing both
dts_fixup.h and per instance Kconfig symbols.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add local-mac-address on DT and enable it on rf2xx driver. If user
define local-mac-address this value will be used as default mac address.
Otherwise driver automatically add a random mac address.
On application level user can change default mac address using net_mgmt
command with NET_REQUEST_IEEE802154_SET_EXT_ADDR parameter defined on
include/net/ieee802154_mgmt.h header.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Replace DT_FLASH_DEV_NAME with DT_CHOSEN_ZEPHYR_FLASH_CONTROLLER_LABEL.
We now set zephyr,flash-controller in the chosen node of the device
tree to the flash controller device.
NOTE: For a SoCs with on die flash, this points to the controller and
not the 'soc-nv-flash' node. Typically the controller is the
parent of the 'soc-nv-flash' node).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Rework the devicetree to utilize new DT_INST macros and extract per
instance data for clocks from devicetree. Move the prescaler setting
from Kconfig to devicetree as well.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add clock references for ADC and TC devices. Update the bindings for
these devices to require clocks property and update the dtsi files to
have the clock info.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Rework the devicetree to utilize new DT_INST macros and extract per
instance data for clocks and dma from devicetree. We update the
atmel,sam0-spi binding for dma to replace the rxdma and txdma
properties with proper 'dmas' property.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Rework the devicetree to utilize new DT_INST macros and extract per
instance data for clocks and dma from devicetree. We update the
atmel,sam0-i2c binding for dma to replace the dma property with
proper 'dmas' property.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add pinctl support for the SAM SPI device. We update the SPI
binding to have pinctrl-0 bindings that are expected to have
at least phandles for MISO, MOSI, and SPCK, but might also have
various chip selects as well.
The pinctrl nodes will have an 'atmel,pins' property that describes the
GPIO port, pin and periphal configuration for that pin.
We update sam*-pinctrl.dtsi files with all the various pin ctrl
configuration operations supported by the given SoC family. These
files are based on data extracted from the Atmel ASF HAL
(in include/sam<FAMILY>/pio/*.h).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add wdt0 node labels for all watchdogs. Keep the existing wdt node
labels in place for backwards compatibility.
Add a wdt1 node to the nRF5340 application core .dtsi, but leave it
disabled. Leave the wdt node's label set to "WDT" on this core for
backwards compatibility also, in case any users are getting it with a
string literal instead of asking the devicetree. This can be changed
later after this round of watchdog changes has been shaken out and
tested more.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The SAM D5x and E5x series SoCs include the "Cortex-M4F" core, not the
FPU-less "Cortex-M4" core.
This commit fixes the incorrect CPU compatible for the SAM D5x and E5x
SoCs (note that this file is included by `same5x.dtsi`, which is used
as the base device tree header for the SAM E5x series).
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Adding port information for uart tx and rx pins in dts, so that it can
be more systematically retrieved in the uart driver.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
Convert driver to use DT_INST_ defines. As part of this conversion we
remove the Kconfig options for per GPIO controller enables and instead
get that information from device tree. This means we now disable each
GPIO controller by default in the DTS and have each board dts enable the
GPIO controller ports it needs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Reworked adc_sam_afec driver to utilize new DT_INST macros as part of
this rework we also now get pin ctrl/mux configuration information
from the device tree instead of via Kconfig and defines in soc_pinmap.h
We remove defines from dts_fixup.h and soc_pinmap.h and associated
Kconfig symbols that are no longer needed due to getting all that
information from devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Rework the devicetree to utilize new DT_INST macros and extract per
instance data for clocks and dma from devicetree. We update the
atmel,sam0-uart binding for dma to replace the rxdma and txdma
properties with proper 'dmas' property.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move the atmel,sam0-dmac binding under the dma binding dir and add
cell information for channel and trigger source. Update the associated
dtsi files to match these changes.
This is in prep of ATMEL SAM0 SERCOMM devices like UART, I2C, and SPI to
user proper 'dmas' property to specify the dma info to use.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add support for the GCLK, MCLK, and PM clock controllers. Add bindings
and devicetree nodes associated with these clock controllers. Also add
clock references for the SERCOM peripheral set to allow those drivers
(i2c, spi, uart) to utilize this information.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit renames `samd.dtsi` to `samd2x.dtsi` since this DTS header
is specific to the SAM D2x series and its derivatives (e.g. SAM R21).
Note that the SAM D5x series uses a different DTS header file (i.e.
`samd5x.dtsi`) due to the vast differences, and the future SAM D1x will
have to use a separate DTS header to be sensible anyway.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
