The generic SPI GPIO chip select support now respects devicetree flags
for signal active level. Update all cs-gpios properties to specify
active low.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
We deprecated a number of aspects of the DTS binding syntax in Zephyr
2.1. Remove the support for the deprecated syntax. Remove from docs
about the deprecated syntax as well.
Removed reference in release-notes-2.1.rst to legacy_binding_syntax
since that anchor doesn't exist anymore.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
compatible = "arm,cortex-m33f" was already used for some time
(lpc55S6x, nrf9160...) without any related bindings.
Every works fine until you need to access one CPU node property
(eg. clock-frequency)...
Signed-off-by: Arnaud Mouiche <arnaud.mouiche@invoxia.com>
Several peripherals are non-functional in the ENG_A revision
of nRF5340 (Application MCU) so we delete the corresponding
DTS nodes in the device description.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Rename the nRF5340 QKAA variant .dtsi headers (Application
MCU) by adding an Engineering A (Eng A) suffix. This is done
to indicate that the headers should be explicitly used when
building for a board that contains the Engineeering A nrf5340
SoC variant.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We need to use CPUAPP and CPUNET instead of CPU0 and CPU1
terminology, because those terms are the ones used
throughout the DeviceTree definitions for nRF5340 SoC.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Move the definition of the number of MPU regions
(num-mpu-regions) in a SoC variant-specific header
instead of the common .dtsi for nRF5340 Application
MCU. This allows us to define different SoC variants
with different number of MPU regions available.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit renames the nrf5340_cpuapp_common.dtsi header
to nrf5340_cpuapp_peripherals.dtsi. This name is more
appropriate, as the header contains DT definitions for
peripherals, accessible from either Secure or Non-secure
execution environment (i.e. not accessible exclusively
by Secure or Non-Secure).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit adds the device tree TCC (Timer/Counter for Control
Applications) peripheral definitions for the Atmel SAM D5x and E5x
series SoCs.
The SAM D5x/E5x series SoCs have five instances of the TCC peripheral:
TCC# Channels Waveform Output Counter Size
0 6 8 24-bit
1 4 8 24-bit
2 3 3 16-bit
3 2 2 16-bit
4 2 2 16-bit
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Add support for STM32L0X using the generic STM32 backend. This is
quite a significant change since the L0 series uses a slightly
different flash controller. Refactor the generic backend to better
support different block sizes and the L0's register interface.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
Add device tree bindings for the Semtech SX1261 and SX1262
radios. These will be used by Zephyr's LoRa drivers.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
Adds optional device tree properties to set delays between spi chip
select assert/deassert and clock edges in the mcux dspi and lpspi
drivers. If these properties are not set, then the minimum supported
delays are used.
Verified that tests/drivers/spi/spi_loopback/ still passes on
mimxrt1050_evk (lpspi driver) and frdm_k64f (dspi driver).
Measured with a scope that the pcs-sck-delay and sck-pcs-delay times on
the first spi transaction in the test are reduced from 7.82 us to 20 ns
on mimxrt1050_evk.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Add Nuvoton numicro series UART support, currently supports
only poll mode.
UART0 clock and pincontrol are directly configured, will be
replace when clock and gpio support is added.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
Add initial support for nuvoton numicro m48x SoC series, basic
init and uart functionality are covered with gpio and clock
directly relies on HAL.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
The SAMD21 series has three timer/counters with a mix of channels and
resolutions. Note that the SAMD20 only has TC peripherals and no TCC
peripherals which is why the changes are in samd21.dtsi.
Signed-off-by: Michael Hope <mlhx@google.com>
The SAM0 Timer/Counter for Control Applications can act as a counter
or generator. Add a binding for the TCC in PWM mode and helper to
check the compat mode.
Signed-off-by: Michael Hope <mlhx@google.com>
Timer interrupts have been added for all STM32 SoC. H7 series already
had the interrupt definitions. The IRQ number and names have been taken
from the STM32Cube HAL header files.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The value of a label property isn't really the name of an API. It's
the name of a device, as passed to device_get_binding().
Let's just say that directly so people know what this means in
practice instead of what's currently used as the description, which is
harder to understand and not really accurate.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
RF SPDT switches used for RX/TX selection have often power enable pin
connected to MCU's GPIO, so it is possible to disable it to save power
when not doing any data transfers. Add 'antenna-enable-gpios' property
to support such designs.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Add support for TCXO power control using GPIO pin. Some boards
(including B-L072Z-LRWAN1 already supported in Zephyr) need delay
applied after powering on TCXO, so add device-tree property allowing to
configure that as well. Cache information about TCXO power status, so
subsequent requests to enable it will not result in unnecessary delays.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
There are several antenna path designs on SX1276 compatible boards in
the wild. B-L072Z-LRWAN1 board has dedicated enable pins for RFI, RFO
and PA_BOOST. This is exactly what this patch allows to
configure. Second variant of antenna selection is done with a single
GPIO pin, which controls RF SPDT switches (input or output). This is
also supported, when either 'rfo-enable-gpios' or
'pa-boost-enable-gpios' property is provided alone (RFO/PA_BOOST is
selected only when transmitting, so there is no need for explicit
'rfi-enable-gpios' configuration).
Drop requirement for 'power-amplifier-output' DT property when there is
either 'rfo-enable-gpios' or 'pa-boost-enable-gpios' configured. Fail
using BUILD_ASSERT() when neither is specified.
Make the SX1276SetAntSw() logic similar to loramac-node examples
implementation, so RFO/PA_BOOST is enabled only in
RFLR_OPMODE_TRANSMITTER.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
PA selection mainly depends on board design. So it looks like
device-tree is a better mechanism than Kconfig in this case. Use string
property with two possible values: "rfo" and "pa-boost".
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
With addition of flash_get_parameters API call, it is needed to provide
support for the API to flash drivers.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
Add support for the polarity flag in the STM32 PWM driver.
STM32 boards using PWM have been updated accordingly.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Aliases defined for peripheral nodes in the nRF SoC definitions were
used in drivers to properly match the hardware instances.
After the drivers were converted to use the new DT API, these aliases
became needless.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Previously, DTS specification of physical RAM bounds did not
correspond to the actual bounds of system RAM as the first
megabyte was being skipped.
There were reasons for this - the first 1MB on PC-like systems
is a no-man's-land of reserved memory regions, but we need DTS
to accurately capture physical memory bounds.
Instead, we introduce a config option which can apply an offset
to the beginning of physical memory, and apply this to the "RAM"
region defined in the linker scripts.
This also fixes a problem where an extra megabyte was being
added to the size of system RAM.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Appropriate WS can be loaded automatically if
the display controller has integrated temperature
sensor or an external sensor is connected.
Signed-off-by: Johann Fischer <j.fischer@phytec.de>
Enable GPIO as a workaround to enable some SPI slaves are not correctly
controlled using the Flexcomm SPI device.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
Those MCUs have 2KB RAM and 16KB FLASH memory, but they are still
powerful enough to run small configuration of Zephyr RTOS.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
- Change default CPU Clock to 240MHz
(PLL is activated)
- I2C, UART will use sysclk from clock driver
- esp32_enable_peripheral replaced by
clock_control_on
Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
- Support PLL for Higher Frequencies 80,160,240 MHz
- Support XTAL Frequencies 26MHz, 40MHz
- Clock Driver can't be disabled, because all of the other drivers
will depend on it to get their operating Frequency based on chosen
clock source (XTAL/PLL).
- Add needed references to BBPLL i2c bus ROM functions.
- Add `rtc` node to Device Tree.
- Since All Peripherals Frequency is depending on CPU_CLK Source,
`clock-source` property added to CPU node
Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
Cleaned up flow control configuration. Added support for using only
cts or only rts.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
The STM32L072 and STM32L073 comes with a hardware random number
generator. Add this to the device tree.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
This allows referencing the CPU in the board-specific DTS file.
Also fix warnings by making the addresses lower case.
Signed-off-by: Michael Hope <mlhx@google.com>
