- The boards\arm\cy8cproto_063_ble board now has ADC enabled
- This includes overlay files for the test app and sample app
Signed-off-by: Bill Waters <bill.waters@infineon.com>
This driver implement basic functions of ili9342c controller
which comes mostly with IPS displays.
Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
The LSM6DSV16X is a system-in-package featuring a 3-axis digital
accelerometer and a 3-axis digital gyroscope for industrial and IoT
solutions. The LSM6DSV16X embeds advanced dedicated features such as
a finite state machine (FSM) for configurable motion tracking and a
machine learning core (MLC) for context awareness.
https://www.st.com/en/mems-and-sensors/lsm6dsv16x.html
This driver is based on stmemsc HAL i/f v2.02
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Convert the NPCX keyboard scan driver to the input subsystem and add the
input to kscan compatibility driver to maintain functionality with the
current API.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add a USB device controller driver skeleton to use as a starting point
for implementing a specific driver.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Example configuration uses 'A' and 'X' key codes for longpress events.
Described behavior shows correct key codes (30 and 45), however comments
near those key codes were invalid for 'X' key. Fix that.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Glitches were observed if a GPIO pin was configured by
ROM to a non-default state and then Zephyr PINCTRL
reconfigured the pin. The fix involves using the correct
PINCTRL YAML output enable and state flags. Reading the
current spin state and reflecting into new pin configuration
if the pin is output and the drive low/high properties are
not present. We also take advantage of GPIO hardware reflecing
the alternate output value in the parallel output bit before
enabling parallel output mode. Interpret boolean flags with
both enable and disable as do not touch if neither flag is
present. We give precedence to enable over disable if both
flags mistakenly appear. Note, PINCTRL always clears the
GPIO control input pad disable bit.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
The ACE 2.0 LNL platform has 5 HIFI4 cores. Change number
of cores to enable 5th core on the platform.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
Added i-cache-line-size and d-cache-line-size values
to device tree for ace20_lnl platforms. These values
are used by sys_cache_instr_line_size_get and
sys_cache_data_line_size_get functions.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
Allows Ethernet communication between "cells"
in the Jailhouse hypervisor.
The vring queue deviates from a standard virtqueue
so is implemented separately.
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
This allows finding the correct PCIe device when multiple devices
have the same vendor-id/device-id but differ in the class-rev register
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
Add support for partial refresh profiles. This makes it possible to
use partial refresh on generation 2 devices which are able to store
partial refresh LUTs in OTP.
Partial refresh is only enabled if a partial profile has been
provided. The display will use the full refresh profile if in this
case.
Devices that need custom LUTs and voltages can specify them separately
for the full and partial profiles. The controller will be reset when
changing profiles which means that profiles always override the
default reset values. This means that it is, for example, possible to
use default values and LUTs from OTP for a full refresh and a custom
profile for partial refreshes.
For example, to use a GoodDisplay GDEY027T91 with partial refresh
simply use the following device tree fragment:
display: ssd1680@0 {
compatible = "solomon,ssd1680";
spi-max-frequency = <4000000>;
duplex = <SPI_HALF_DUPLEX>;
reg = <0>;
dc-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>;
reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>;
busy-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>;
/* Enable the built-in temperature sensor */
tssv = <0x80>;
width = <264>;
height = <176>;
/* Enable partial refresh using built-in LUT */
partial {
};
};
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Update the device tree bindings for the SSD16xx driver to make it
possible to specify multiple refresh profiles.
The only profile currently supported is the 'full' profile.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
The SSD16xx driver currently provides basic support for most chips in
the Solomon Systech SSD16xx range of e-paper drivers. We currently use
the SSD1608, SSD1673, SSD1675A, and SSD1681 in various boards
supported by Zephyr.
The main user-facing difference between the various SSD16xx chips is
the resolution they support (sources & gates), but there are other
differences as well. For example:
* 8 or 16 bits used to represent x coordinates
* 8 or 16 bits used to represent y coordinates
* Differences in refresh configuration (SSD16XX_CMD_UPDATE_CTRL2)
* Differences in LUT sizes
The driver currently assumes that the user specifies the number of
bits used to describe coordinates. However, as we add support for more
chips, more of the differences will become apparent and need
workaround.
Comparing data sheets from different chips in the SSD16xx range
suggests that there are (at least) two different generations
present. These differ in the size of the LUTs they expect and the way
they handle partial refresh. This impacts register layout where
SSD16XX_CMD_UPDATE_CTRL2 uses bit 3 selects "mode 2" whereas older
devices uses this for a mode referred to as "initial".
In order to add support for partial refresh in newer devices, we need
to be able to distinguish between the different generations of the
chip. It might be possible to add a DT property to indicate the
revision, but that seems like a bit of an anti-pattern and it would be
hard for users to specify the correct chip generation.
This change introduces chip-specific compatible strings instead of the
generic SSD16xx. There is unfortunately clear pattern that can be used
to distinguish different generations, so the full chip name must be
specified. A benefit of this is that we don't need to specify the
width of the fields describing coordinates in device trees.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Add RT1040 SOC devicetree. This devicetree removes IP blocks absent on
the RT1040, and configures clock dividers correctly for the RT1040's
clock tree
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Fix PINT base address for LPC51xxx and 54xxx. These addresses were
incorrectly copied from the LPC55S69, which utilizes trustzone. Add the
relevant base address offset to the addresses.
Fixes#57334
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Use the same wording in description for both I2C and SPI variants to
improve consistency.
Create st,lsm6dsl-common.yaml to include common binding properties from I2C
and SPI variants.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Update LTDC driver to use LCDIF bindings, to simplify bindings
between LCD interface controller IP blocks.
Boards supporting the LTDC are also updated to use the properties as
declared by the new lcd controller binding
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update MCUX ELCDIF driver to use new LCDIF bindings. This
update also adds support for configuring the root clock of
the ELCDIF module based on the pixel-clock property to the
RT11xx SOC clock init, as this SOC series has this IP block
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update DCNANO LCDIF IP to use shared lcd interface binding. This
requires changes to the RT5xx SOC and RT595 EVK, as this SOC
uses the LCDIF IP, and configures the clock for it based off
the new pixel-clock property.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add common LCD interface binding. This binding captures the
following properties, which are shared between multiple LCD interface
IP blocks:
- VSYNC/HSYNC pulse width
- Vertical/Horizontal front and back porch
- HSYNC,VSYNC,data enable, and pixel clock polarity flags
- pixel clock frequency
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce phy-clock property, which is used by MIPI devices to determine
the target clock frequency for the MIPI PHY. This property can vary
depending on the attached display and target framerate.
Update the MIPI DSI MCUX driver to utilize this property to configure
the MIPI host, and update the RT500 clock initialization to configure
the MIPI root clock based on this property.
Remove dphy-clk-div property from the MIPI DSI 2L binding, as it
is redundant with this change.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Let the Bosch M_CAN front-end drivers supply their own register read/write
functions.
This is preparation for handling non-standard Bosch M_CAN register layouts
directly in the front-end and for accessing Bosch M_CAN IP cores over
peripheral busses.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Currently, the usb_dc_dw driver is not enabled for any platform.
Allow to build the driver for cyclonev_socdk. Subsequent patches
will allow the driver to be used on additional platforms.
Enable USB device controller and use use new snps,dwc2 compatible.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Although snps,designware-usb bindings already exist, this one is
prolematic. Compatible is too general and does not reflect
the actual controller IP. It has Zephyr-specific properties,
but has no zephyr prefix. It forces properties that are not
necessary for this controller. We start here with new bare minimum
properties for DesignWare OTG USB 2.0 controller.
The STM32F4 SoC family USB controllers, which are also implement
DesignWare OTG USB 2.0 IP, can also be used with existing drivers,
but require certain quirks. To use these we need special compatible.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add GDMA support for esp32s3.
Remove suspend/resume since they are optional and do
the same as start/stop.
Fix possible null pointer derreference.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Declare SCB nodes to be used as UART/SPI/I2C by the boards, Move
common declarations from psoc6_02 to the parent dtsi file
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
