The controller and the driver support two hardware configurations:
- one three-channel (RGB) LED
- or three single-channel LEDs
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
Some boards may have connected the enable pin of the chipset to a GPIO.
On these boards, it is necessary to configure and set this GPIO before
using the chipset, otherwise the I2C circuitry is disabled.
Based on initial work from:
- Marek Janus <marek.janus@grinn-global.com>
- Rico Ganahl <rico.ganahl@bytesatwork.ch>
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
Add support for LP5009, LP5012, LP5018 and LP5024 devices which only
differ by the number of LEDs they can control.
Also, update application sample to run on all these new supported
devices.
Based on initial work from:
- Marek Janus <marek.janus@grinn-global.com>
- Rico Ganahl <rico.ganahl@bytesatwork.ch>
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
This commit addst support for the system timer peripheral which
can be found in Apollo4 SoCs.
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
UART controllers present on Ambiq SoCs implement a PL011 compatible
interface, with some minor differences that require certain quirks.
To support them a dedicated compatible is needed.
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
This commit addst pinctrl support for Apollo4 SoCs.
Co-authored-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
Adds a new I2C shim driver for Intel SoCs. Builds upon the SEDI bare
metal I2C driver in the hal-intel module.
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
Sometimes, channel C may write wrong register to the target device.
This issue occurs when FIFO2 is enabled on channel C. The problem
arises because FIFO2 is shared between channel B and channel C.
FIFO2 will be disabled when data access is completed, at which point
FIFO2 is set to the default configuration for channel B.
The byte counter of FIFO2 may be affected by channel B. There is a
chance that channel C may encounter wrong register being written due
to the FIFO2 byte counter wrong write after channel B's write operation.
The current workaround is that channel C cannot use FIFO mode.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The system still takes both prefixed and unprefixed dt-bindings files,
but let's use zephyr/ prefixed in the examples and documentation.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
On ACE a seperate, soc specific, interrupt mask needs to be enabled
to unmask the interrupt. Do so for GPDMA.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
SPI driver is current working for common SPI devices.
However, addressable LED like WS2812 requires MOSI line to be
default LOW during initialization. This PR adds such option.
This has no effect on common SPI operation.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Modify the NPCX driver erase method to allow 0x1000 byte size erases
along with 0x10000 byte size erases based on input parameters
Signed-off-by: Madhurima Paruchuri <mparuchuri@google.com>
This device has a single instance of EMAC (a 100Mbps version of GMAC).
TCP/UDP checksum calculation is offloaded.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Add initial support for NXP S32 GMAC/EMAC:
- it's a copy-implementation with DMA data buffers and buffer
descriptors in non-cached memory (buf len and ring size configurable)
- PHY interface selection only implemented for S32K3 devices as it is
SoC-specific
- no PHY driver integration, it works as a fixed link with speed/duplex
configured through devicetree
- supports multicast hash filtering, promiscuous mode, MAC loopback
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Change the eth-phy definition so that the phy is pointed by a phandle
rather than a child node, make the phy device a child of mdio. This
makes more sense from a devicetree hirearchy where the phandles have to
be initialized before the device itself, allows keeping the priorities
in check with CHECK_INIT_PRIORITIES.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Make ethernet phys childs of the mdio device and move the mdio device up
a level on the tree. That makes the device hierarchy coherent with the
required initialization priority and allows keeping the sequence in
check with CHECK_INIT_PRIORITIES.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add option to use (by defining the `wake-gpios` devicetree properties)
an additional signal line between SPI master and SPI slave that allows
the latter to stay in low-power state and wake up only when a transfer
is to occur.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Introduce support for NXP FS26 SBC watchdog. Both Challenger and
Simple watchdog types are supported. Only watchdog functionalities of
the device are supported and any other monitoring feature is either not
supported or disabled.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Reuse existing NXP LPSPI binding for this SoC since the hardware block
for this device is the same as the one supported for other NXP devices.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
It's used to pass right device index to hal_intel module.
DT_INST_FOREACH_STATUS_OKAY() does not guarantee the node ordering.
Signed-off-by: Dong D Wang <dong.d.wang@intel.com>
Rename the phy-dev property with phy-handle to match the Linux
ethernet-controller binding and move it up to ethernet.yaml so that it
can be used by other drivers.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Adds a new serial shim driver for Intel SoCs. Builds upon the SEDI bare
metal UART driver in the hal-intel module.
Signed-off-by: Nachiketa Kumar <nachiketa.kumar@intel.com>
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
Add support ADC SAR for NXP S32. ADC SAR diver
support 3 group channels (precision, standard
and external), run normal trigger in oneshot
conversion mode with 2 callbacks normal end
of conversion and normal end chain callbacks.
An instance only run on 1 group channel and
1 kind of callback at the same time.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Enable SPI SDHC driver to manage card power via pwr-gpios property.
Control for this property was previously partially implemented. When
this property is present, the SPI SDHC driver will use it to control
power to the SD card.
Power is toggled during SD init, so this power control can make SD init
more reliable as the power toggle will insure the SD card state is reset.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add driver for HX8394 TFT LCD controller. This controller is driven via
MIPI DSI, and is configured for a 720x1280 display
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
So far pin identifiers were named after CN7 and CN10 connector names on
Nucleo-64 boards. In case of Nucleo-144 there are ST Morpho connectors on
both sides, but bigger (up to 72 instead of 38 pins on each side). First 38
pins out of 72 on each side usually map to the same pins (e.g. PA5 being
13th pin on right ST Morpho connector). This means that single ST Morpho
connector definition will suffice.
Leaving CN7 and CN10 (name of pin headers on Nucleo-64 boards) is confusing
in context of Nucleo-144 boards, since corresponding pin headers are named
CN11 and CN12.
Rename:
* s/ST_MORPHO_CN7_/ST_MORPHO_L_/
* s/ST_MORPHO_CN10_/ST_MORPHO_R_/
so that pin identifiers make more sense in context of Nucleo-144 boards.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Update to shim driver compatible with the hardware block
in S32K344. Configure the pins before initializing I2C
to avoid happening bus busy.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Reuse existing MCUX-based shim driver for FlexCAN.
Enable flexcan0 for Zephyr canbus to run tests.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Devicetree specification v0.4, Section 2.3.1:
"The compatible string should consist only of lowercase letters, digits
and dashes, and should start with a letter."
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
This state is never used in practice, even if handled by the PM
subsystem hooks. Shutdown-like states are always invoked manually, so
they don't need to be described in DT.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
