Kconfig allowed selecting any bit in the status register as the QE
bit, and defaulted it to 6. Devices need not require a QE bit at all,
and where JESD216 defines QE bit location the only place in first SR
byte that it can be is bit 6. Further, the code unconditionally wrote
the value 0x40 without respecting configuration of other bits. Some
of those bits control write protection of block-protected areas and
should not be changed.
Remove the Kconfig, instead using the jedec,jesd216-controlled
devicetree property. Allow the driver to recognize whether or not
setting the bit is required, and when it is only use bit 6. Only
update if the setting does not match the configuration.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
DW15 provides information on entry and exit from QSPI modes. In
particular, it specifies whether and how the status register must be
updated for this feature.
Add a JESD216 devicetree property for the Quad Enable Requirements
value.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Add definitions for UART1/2 when they're accessible through fixed MMIO
addresses (instead of PCIe), and mark all UARTs not normally available
with the UEFI BIOS as "disabled".
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The existing method of testing for any of the first four DT instances
having the pcie property feels a bit clumsy and will get more so when
support for more than four UARTs is added. A much more cleaner way to
do this (and more correct probably as well) is to list any PCIe-based
UART nodes under a pcie bus in the Device Tree hierarchy.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Add a binding to represent a PCIe bus. This way PCIe devices can be
ordered under a parent PCIe bus object and make help of DT BUS macros
for conditional code.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Part of GPIO pads in npcx series support low-voltage (1.8V) level
detection. In order to introduce this feature, this CL adds a new
NPCX-specific controller property, lvol_io_pads, in devicetree file.
For example, here is devicetree fragment which turn on low-voltage
support of i2c1_0 port.
/ {
def_lvol_io_list {
compatible = "nuvoton,npcx-lvolctrl-def";
lvol_io_pads = <&lvol_io90 /* I2C1_SCL0 1.8V support */
&lvol_io87>; /* I2C1_SDA0 1,8V support */
};
};
Then these pads will turn on 1.8V level detection during initialization.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Firmware implementing the PSCI functions described in ARM document
number ARM DEN 0022A ("Power State Coordination Interface System
Software on ARM processors") can be used by Zephyr to initiate various
CPU-centric power operations.
It is needed for virtualization, it is used to coordinate OSes and
hypervisors and it provides the functions used for SMP bring-up such as
CPU_ON and CPU_OFF.
A new PSCI driver is introduced to setup a proper subsystem used to
communicate with the PSCI firmware, implementing the basic operations:
get_version, cpu_on, cpu_off and affinity_info.
The current implementation only supports PSCI 0.2 and PSCI 1.0
The PSCI conduit (SMC or HVC) is setup reading the corresponding
property in the DTS node.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Move iis2dlpc trigger pulse configurations from Kconfigs to Device Tree.
Moreover the dts properties have been renamed as 'tap', which sounds a
better name to immediately catch the feature behind it. Since tap
threshold cannot be zero, this value (which is the default in dts
binding) is used to enable/disable the device feature per each axis.
The event can be generated on INT1 only.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The IIS2DLPC drdy interrupt can be routed to either INT1 or
INT2 pin. Currently the selection is done by Kconfig configuration.
This commit is instead moving it into Device Tree as 'drdy-int'.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The BBC micro:bit v2 is a mini-computer that has been
designed to make the coding fun and easy to learn.
The micro:bit v2 is completely programmable so you can
easily bring your ideas to life! From making games to
creating music and even controlling robots.
The micro:bit comes with neat hardware such as a 25 LED
display, buttons, in-built speakers, Bluetooth 5 & Mesh
connectivity and sensors for temperature, motion & light.
Signed-off-by: Lingao Meng <menglingao@xiaomi.com>
This property is required information for extracting PSEL bits relevant
to peripheral pinmux from this node.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Add some details to help new users learn how to manage the nodes
for compatibles corresponding to IP blocks on Nordic SoCs.
The focus is on IP blocks where the pinmux is configured in
devicetree. These typically have individual properties for each pin,
like a SCK pin on a SPI peripheral, which correspond directly to a
PSEL register value. These violate the usual devicetree convention of
using a 'foo-gpios <&gpioX ...>' phandle property and work in ways
that only make sense if you understand the underlying register map, so
it's worth explaining them a bit more carefully.
Skip these two bindings, which have no drivers: nordic,nrf-i2s.yaml,
nordic,nrf-pdm.yaml.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The QEMU RISC-V VirtIO board is capable:
- 8 x CPU
- 256 MiB RAM
- PMP
- PCI
- ISA string: RVnnIMAFDCSU
- mul/div
- FPU with double precision
- MMU
- Compressed instructions
Devicetree was extracted from QEMU as described in virt.dtsi.
The same .dtsi SOC description is used for 32-bit and 64-bit.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
'reg' attribute removed from overall stm32l1 dts,
so eeprom size has to be specified for each SoC
in stm32l1x series.
Adds remaining stm32l1x SoCs that didn't have eeprom size specified yet.
Eeprom size added in stm32l151Xb-a & stm32l151X8-a dtsi files,
(based on device overview in datasheet DocID024330 Rev 5).
Eeprom size added in stm32l151Xb dtsi file (based on
device overview in datasheet DocID17659 Rev 12).
Signed-off-by: Noelle Clement <noelleclement@hotmail.com>
In npcx7 series, the Timer and Watchdog module (TWD) generates the
clocks and interrupts used for timing periodic functions in the system.
It also provides watchdog reset signal generation in response to a
failure detection.
The CL also includes:
— Add npcx watchdog device tree declarations.
— Zephyr watchdog api implementation.
— Add Watchdog definitions for npcx7 series in
tests/drivers/watchdog/wdt_basic_api/src/test_wdt.c for
supporting test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
This commit is about the it8xxx2 i2c master driver which
includes six SMBus channels. The enhanced channel i2c3,
i2c4, i2c5 are controller which are designed to support
the I2C protocol.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
In order to ease reuse on other series, set DMA as optional
and use IT if no DMA channel is specified in the qspi node.
Tested on disco_l475_iot1
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add device tree description for qspi node on STM32L4 and
signals on whole family.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Setting clock-frequency as required (the driver does not build without
it) and dropping definitions that are already specified in
i2c-controller.yaml.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Replace few instances of space before colon in the binding files, not
functional, just for coherency.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
STM32L152xC SoC differs from other L1 SoCs in RAM (32KiB) and
flash (256KiB) size, EEPROM size (8Kib) and amount of interrupts
(57, see STM32Cube). Devicetree and Kconfig support.
Signed-off-by: Noelle Clement <noelleclement@hotmail.com>
after 7c699348a8
Convert drivers to new DT device macros
now the device name is aligned with label so we need
align them to default config
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
This patch adds IRQ priority support for SiFive PLIC by device-tree.
Some IRQ sources of plic use Kconfig to set priority of their IRQ.
- AON: no driver
- I2C, SPI, PWM: not use IRQ
- GPIO, UART: default 1
So this patch specifies IRQ priority 1 for all sources.
Currently these drivers (gpio and uart) do not support that they get
and use IRQ priority from device-tree. We need more patches.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
The npcx7m6fb dts defines i2c controller and ports, where the controller
is a property in the port node definition and the device nodes should be
defined as subnodes of the port.
This changes the binding definitions to reflect that, defining the port
as an i2c-controller so that in can inherit sub-nodes for i2c devices,
and the controller as a generic node.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
jedec,jesd216.yaml has properties for any memory device that conforms
to the JESD216 specification. This file at a minimum should be
included in the binding for any driver that interacts with such a
device.
jedec,spi-nor-common.yaml extends jedec,jesd216 with additional
parameters useful for memory devices that are not available from
standard JESD216 parameter tables. This file may be included instead
of jedec,jesd216.yaml if a driver is able to support additional
functionality related to the extended description.
jedec,spi-nor.yaml remains the binding for the Zephyr SPI_NOR driver
alone.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Add binding for the Nordic ECB (AES electronic codebook mode
encryption) peripheral and corresponding devicetree nodes for
nRF SoCs that feature this peripheral.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Since MDK was updated and now it contains the definition of QDEC
peripheral for nRF52805, the DT node representing this peripheral
can be processed normally.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
"st,mem2mem" property is supposed to be limited to dma-v1.
Remove its use in dma-v2 components.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2 versions of DMA hardware blocks could be found across stm32 series.
In order to simplify the handling of matching Kconfig symbols,
make this visible in dts files by creating "st,stm32-dma-v1" and
"st,stm32-dma-v2" and set them accordingly in dtsi files.
Duplicate and update related bindings to reflect that new state.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Tigerlake H has less RAM and fewer cores. Both should be
supported, selectable at the board level. For now use the H
configuration as more readily available for testing.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
The STM32F105xx is effectively an STM32F107xx without Ethernet. As such,
it's possible to include the STM32F105's device tree from STM32F107, and
add in any additional nodes (currently just DMA2, though according to
the datasheet, this may be supported by the STM32F105xx and other parts
too).
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
