The `cpu-power-states` property needs to be defined at SoC dts files,
since it's a property of the SoC, not board.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Adds driver for pwm on xmc4xxx using Capture Compare Unit 8 (CCU8)
module. There are two CCU8 nodes with each one having four slices.
Each slice has two output channels.
Unlike CCU4, this module can generate complementary high-side/low-side
signals for each output channel. A variable dead time can be added
during the off to on transitions to make sure that the
high-side/low-side signals are not on at the same time.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Adds driver for pwm on xmc4xxx using Capture Compare Unit 4 (CCU4)
module. There are four CCU4 with each one having four channels
Thus it's possible to have up to 16 pwm output signals. The output of
each channel can only be connected to a specific port/pin. The possible
connection and gpio configurations are defined using pinctrl.
The CCU4 module also has a capture mode. Capture support will be added
in the future.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Add mailbox and interrupt-controller nodes used for
inter-process communication.
Add also the dt binding for the interrupt-controller.
For now, this is used just to fix some compile errors,
since the mailbox requires an interrupt-controller.
For DSP, we have a direct interrupt line to the core.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Introduces support for SoC-specific input-edge-detect configuration to
the CC13/26xx pinctrl driver.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
Added a driver for the DFRobot A01NYUB distance sensor. This sensor
sends its readings via UART at 9600 baud. This driver uses interrupts
to read the data from the sensor.
Signed-off-by: Oliver King <oliver.king@steadconnect.com>
Add support for flash NOR memory devices on a NXP S32 QSPI bus. The
driver uses a fixed LUT configuration assuming a default standard page
size and erase types, and allows to select between multiple read/program
instructions/modes. It is also possible to read the flash device
characteristics from the device at run-time as long as the memory is
JESD216 compatible, providing more flexibility.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The NXP S32 QSPI controller acts as an interface to up to two serial
flash memory devices, each with up to eight bidirectional data lines,
depending on the platform. It is based on a LUT enginee to interface
through commands with different memory types including flash NOR and
Hyperram.
This patch adds support for the QSPI in S32K344 which supports a single
memory device (side A) with up to four bidirectional data lines and SDR
only. Nevertheless, the memory controller is implemented flexible enough
to be extended to support more feature-rich QSPI blocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit aligns TWIM shim to utilize memory-region property.
The memory-region is not required property that enables user
to specify placement of dma buffers in memory region.
It is done by assigning to memory-region property,
phandle to node with zephyr,memory-region and mimo-sram compatible.
When memory-region property is not specified for given
instance, buffer is placed in default RAM region with other data.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
Add initial version of Infineon CAT1 counter driver
Add initial version of binding file for Infineon
Add counters to psco6 dtsi
Add external trigger pin that runs counter
Signed-off-by: Pavlo Havrylyuk <pavlo.havrylyuk@infineon.com>
Each PSCI interface versions have different DT compatible strings
like arm,psci-0.2, arm,psci-1.1 and so on. However, the same driver
can be used for all the versions by adding #define DT_COMPAT for
required version and #undef DT_COMPAT for default version.
Add support for PSCI cold reset, warm reset and cpu-on function IDs.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Navinkumar Balabakthan <navinkumar.balabakthan@intel.com>
If the optional hardware reset line is available, this change
will use that reset line to assert the uart module and bring
it out of reset state to use.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
This is Intel's proprietary IP which controls individual module
reset signals. During each system driver initialization, these
reset signals will be used to bring module out of reset state.
Signed-off-by: Navinkumar Balabakthan <navinkumar.balabakthan@intel.com>
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Device tree for Intel SoCFPGA Agilex5 initial bring up. This is the
first version of device tree which enable four cores SMP and basic
drivers that needed by 'hello_world' and 'cli' applications.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
This is Intel's proprietary IP which supply the clock for all the
system peripherals. Clock manager is initialized only one time
during boot up by FSBL (ATF BL2) based on external user settings.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Introduce dtsi files representing the
current portfolio of chips and modules
based on the:
- flash size
- psram size
- gpio count
- certification status
Update the boards dts files according
to which SOC/SIP they are using.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Introduce dtsi files representing the
current portfolio of chips and modules
based on the followint criteria:
- flash size
- psram size
- gpio count
- certification status
Update the boards dts files according
to which SOC/SIP they are using.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Previously the driver was retrofitted to the kscan api, handling it as a
input device with one row and three columns. With the move to the input
subsystem each input can have its proper input code instead.
Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
The 'zephyr,memory-region-mpu' property was addede gqas a
convenient way to create and configure MPU regions using information
coming from DT. It has been used a lot since it was introduced so I
guess we can consider it a Zephyr success story ™ .
Unfortunately it has been proved to be a bit limited and with some
important limitations:
1. It was introduced as a property of the compatible
zephyr,memory-region that is used to create linker regions and
sections from DT data. This means that we can actually create MPU
regions only for DT-defined regions and sections.
2. The naming is unfortunate because it is implying that it is used only
for MPU.
3. It is misplaced being in include/zephyr/linker/devicetree_regions.h
and still it has nothing to do with the linker at all.
4. It is exporting a function called LINKER_DT_REGION_MPU that again has
nothing to do with the linker.
Point (1) is also particularly limiting because it is preventing us to
characterize memory regions that are not generated using the
'zephyr,memory-region' compatible, like generic mmio-sram regions.
While we fix all the issues, we also want to extend a bit the range of
usefulness of this property. We are renaming it 'zephyr,memory-attr' and
it is now carrying information about the type of memory the property is
attached to (cacheable, non-cacheable, IO, eXecutable, etc...). The user
can use this property and the DT API coming with it to act on the memory
node it is accompanied by.
We are still providing the DT_MEMORY_ATTR_APPLY() macro that can be used
to create the MPU regions as before, but we are adding also a
DT_MEMORY_ATTR_FOREACH_NODE() macro that can be used to cycle through
the memory nodes and act on those.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
CPU idle states are not board specific. This patch moves Nuvoton idle
states to the core SoC dts files. Board can always tweak some state
parameters (if needed), but the definition belongs to core SoC dts
files, same as e.g. peripherals.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
CPU idle states are not board specific. This patch moves NXP idle states
to the core SoC dts files. Board can always tweak some state parameters
(if needed), but the definition belongs to core SoC dts files, same as
e.g. peripherals.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
CPU idle states are not board specific. This patch moves Microchip MEC
idle states to the core SoC dts files. Board can always tweak some state
parameters (if needed), but the definition belongs to core SoC dts
files, same as e.g. peripherals.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
CPU idle states are not board specific. This patch moves TI idle
states to the core SoC dts files. Board can always tweak some state
parameters (if needed), but the definition belongs to core SoC dts
files, same as e.g. peripherals.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
CPU idle states are not board specific. This patch moves STM32 idle
states to the core SoC dts files. Board can always tweak some state
parameters (if needed), but the definition belongs to core SoC dts
files, same as e.g. peripherals.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
CPU idle states are not board specific. This patch moves ESP32 idle
states to the core SoC dts files. Board can always tweak some state
parameters (if needed), but the definition belongs to core SoC dts
files, same as e.g. peripherals.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The NXP Pixel pipeline engine (PXP) is a 2D DMA engine capable of
accelerating display rotation, color space conversion, and limited
2D blending operations. This DMA driver only supports rotation of a
framebuffer, via a set of custom dma_slot values. Only DMA channel 0
is supported or utilized.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Updated the driver to support low power mode.
Introduced "enable-low-power" flag in device tree to
control(on/off) low power mode.
If flag added in DTS, during sleep BBLED will switch off the LEDs.
Otherwise BBLED will continue the configured blinking pattern on LEDs.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Add support for resetting controller at boot, and update FT5336
documentation to indicate that the FT3267 IC is also supported by this
driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for RM67162 MIPI display controller. This controller
is configured to run in MIPI command/DBI mode, driving a 400x392 OLED
display.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Only setup DPI input from LCDIF if MODE_VIDEO is set, as this
is the the only case where input from the LCDIF would be required to
drive the display. Do not populate the dpi_config structure unless a
reference the the NXP LCDIF device is provided, since this is the output
device providing DPI data.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Fixup support for DCS_LONG_WRITE command in DSI MCUX 2L driver. Since long
DCS commands may benefit from nonblocking I/O, add support for non blocking
transfers to the DSI driver.
This commit also corrects the interrupt number for the RT595, which uses
the DSI_MCUX_2L IP block.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Make DPI mode an optional configuration for the DSI MCUX 2L driver.
DPI mode will only be enabled when the MIPI is attached in video mode,
since this is when DPI formatted packets are expected.
This will enable the DSI driver to also support DBI/command mode, for
displays that use this format.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Added dts additions for stm32f105xb cpu which is the same as existing
stm32f105xc with less flash.
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
